CRIS: Remove VCS simulator specific code

The VCS simulator was a tool used in the development of the chip
and is no longer used or necessary.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>

14 files changed, 3 insertions, 435 deletions

diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index bb344650a14f..ca038afb8b5b 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -137,11 +137,6 @@ config CRIS_MACH_ARTPEC3
 
 endchoice
 
-config ETRAX_VCS_SIM
-        bool "VCS Simulator"
-        help
-          Setup hardware to be run in the VCS simulator.
-
 config ETRAX_ARCH_V10
        bool
        default y if ETRAX100LX || ETRAX100LX_V2
diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c
index b34438e026be..1b6ad6247204 100644
--- a/arch/cris/arch-v32/drivers/axisflashmap.c
+++ b/arch/cris/arch-v32/drivers/axisflashmap.c
@@ -329,7 +329,6 @@ static int __init init_axis_flash(void)
         }
 #endif
 
-#ifndef CONFIG_ETRAX_VCS_SIM
         main_mtd = flash_probe();
         if (main_mtd)
                 printk(KERN_INFO "%s: 0x%08x bytes of NOR flash memory.\n",
@@ -603,34 +602,7 @@ static int __init init_axis_flash(void)
                                         "partition %d\n", part);
                 }
         }
-#endif /* CONFIG_EXTRAX_VCS_SIM */
 
-#ifdef CONFIG_ETRAX_VCS_SIM
-        /* For simulator, always use a RAM partition.
-         * The rootfs will be found after the kernel in RAM,
-         * with romfs_start and romfs_end indicating location and size.
-         */
-        struct mtd_info *mtd_ram;
-
-        mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
-        if (!mtd_ram) {
-                panic("axisflashmap: Couldn't allocate memory for "
-                      "mtd_info!\n");
-        }
-
-        printk(KERN_INFO "axisflashmap: Adding RAM partition for romfs, "
-               "at %u, size %u\n",
-               (unsigned) romfs_start, (unsigned) romfs_length);
-
-        err = mtdram_init_device(mtd_ram, (void *)romfs_start,
-                                 romfs_length, "romfs");
-        if (err) {
-                panic("axisflashmap: Could not initialize MTD RAM "
-                      "device!\n");
-        }
-#endif /* CONFIG_EXTRAX_VCS_SIM */
-
-#ifndef CONFIG_ETRAX_VCS_SIM
         if (aux_mtd) {
                 aux_partition.size = aux_mtd->size;
                 err = mtd_device_register(aux_mtd, &aux_partition, 1);
@@ -639,7 +611,6 @@ static int __init init_axis_flash(void)
                               "aux mtd device!\n");
 
         }
-#endif /* CONFIG_EXTRAX_VCS_SIM */
 
         return err;
 }
diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S
index 5d502b9ab56d..51e34165ece7 100644
--- a/arch/cris/arch-v32/kernel/head.S
+++ b/arch/cris/arch-v32/kernel/head.S
@@ -36,13 +36,6 @@
         .global nand_boot
         .global swapper_pg_dir
 
-        ;; Dummy section to make it bootable with current VCS simulator
-#ifdef CONFIG_ETRAX_VCS_SIM
-        .section ".boot", "ax"
-        ba tstart
-        nop
-#endif
-
         .text
 tstart:
         ;; This is the entry point of the kernel. The CPU is currently in
@@ -75,17 +68,10 @@ secondary_cpu_entry: /* Entry point for secondary CPUs */
                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4)     \
                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 5)     \
                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
-#elif !defined(CONFIG_ETRAX_VCS_SIM)
-        move.d  REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8)       \
-                | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4)     \
-                | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
 #else
-        ;; Map the virtual DRAM to the RW eprom area at address 0.
-        ;; Also map 0xa for the hook calls,
         move.d  REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8)       \
                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4)     \
-                | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb)   \
-                | REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa), $r0
+                | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
 #endif
 
         ;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00.
@@ -126,27 +112,6 @@ secondary_cpu_entry: /* Entry point for secondary CPUs */
                 | REG_STATE(mmu, rw_mm_cfg, seg_2, page)        \
                 | REG_STATE(mmu, rw_mm_cfg, seg_1, page)        \
                 | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
-#elif !defined(CONFIG_ETRAX_VCS_SIM)
-        move.d  REG_STATE(mmu, rw_mm_cfg, we, on)               \
-                | REG_STATE(mmu, rw_mm_cfg, acc, on)            \
-                | REG_STATE(mmu, rw_mm_cfg, ex, on)             \
-                | REG_STATE(mmu, rw_mm_cfg, inv, on)            \
-                | REG_STATE(mmu, rw_mm_cfg, seg_f, linear)      \
-                | REG_STATE(mmu, rw_mm_cfg, seg_e, linear)      \
-                | REG_STATE(mmu, rw_mm_cfg, seg_d, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_c, linear)      \
-                | REG_STATE(mmu, rw_mm_cfg, seg_b, linear)      \
-                | REG_STATE(mmu, rw_mm_cfg, seg_a, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_9, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_8, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_7, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_6, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_5, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_4, linear)      \
-                | REG_STATE(mmu, rw_mm_cfg, seg_3, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_2, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_1, page)        \
-                | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
 #else
         move.d  REG_STATE(mmu, rw_mm_cfg, we, on)               \
                 | REG_STATE(mmu, rw_mm_cfg, acc, on)            \
@@ -157,7 +122,7 @@ secondary_cpu_entry: /* Entry point for secondary CPUs */
                 | REG_STATE(mmu, rw_mm_cfg, seg_d, page)        \
                 | REG_STATE(mmu, rw_mm_cfg, seg_c, linear)      \
                 | REG_STATE(mmu, rw_mm_cfg, seg_b, linear)      \
-                | REG_STATE(mmu, rw_mm_cfg, seg_a, linear)      \
+                | REG_STATE(mmu, rw_mm_cfg, seg_a, page)        \
                 | REG_STATE(mmu, rw_mm_cfg, seg_9, page)        \
                 | REG_STATE(mmu, rw_mm_cfg, seg_8, page)        \
                 | REG_STATE(mmu, rw_mm_cfg, seg_7, page)        \
@@ -226,7 +191,6 @@ master_cpu:
         move.d secondary_cpu_entry, $r1
         move.d $r1, [$r0]