drm/i915: Don't read 'HEAD' MMIO register in LRC mode

The logical ring code was updating the software ring 'head' value
by reading the hardware 'HEAD' register. In LRC mode, this is not
valid as the hardware is not necessarily executing the same context
that is being processed by the software. Thus reading the h/w HEAD
could put an unrelated (undefined, effectively random) value into
the s/w 'head' -- A Bad Thing for the free space calculations.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 0 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 047d8f065b99..03b5c04b6ee1 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -986,7 +986,6 @@ static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
         end = jiffies + 60 * HZ;
 
         do {
-                ringbuf->head = I915_READ_HEAD(ring);
                 ringbuf->space = intel_ring_space(ringbuf);
                 if (ringbuf->space >= bytes) {
                         ret = 0;