drm/radeon/kms: add support for Llano Fusion APUs

- add gpu init support
- add blit support
- add ucode loader

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

3 files changed, 116 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 8f446aadccd6..12984a481880 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1433,6 +1433,8 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
         case CHIP_CEDAR:
         case CHIP_REDWOOD:
         case CHIP_PALM:
+        case CHIP_SUMO:
+        case CHIP_SUMO2:
         case CHIP_TURKS:
         case CHIP_CAICOS:
                 force_no_swizzle = false;
@@ -1562,6 +1564,8 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev)
         case CHIP_REDWOOD:
         case CHIP_CEDAR:
         case CHIP_PALM:
+        case CHIP_SUMO:
+        case CHIP_SUMO2:
         case CHIP_TURKS:
         case CHIP_CAICOS:
         default:
@@ -1707,6 +1711,54 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
                 break;
+        case CHIP_SUMO:
+                rdev->config.evergreen.num_ses = 1;
+                rdev->config.evergreen.max_pipes = 4;
+                rdev->config.evergreen.max_tile_pipes = 2;
+                if (rdev->pdev->device == 0x9648)
+                        rdev->config.evergreen.max_simds = 3;
+                else if ((rdev->pdev->device == 0x9647) ||
+                         (rdev->pdev->device == 0x964a))
+                        rdev->config.evergreen.max_simds = 4;
+                else
+                        rdev->config.evergreen.max_simds = 5;
+                rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
+                rdev->config.evergreen.max_gprs = 256;
+                rdev->config.evergreen.max_threads = 248;
+                rdev->config.evergreen.max_gs_threads = 32;
+                rdev->config.evergreen.max_stack_entries = 256;
+                rdev->config.evergreen.sx_num_of_sets = 4;
+                rdev->config.evergreen.sx_max_export_size = 256;
+                rdev->config.evergreen.sx_max_export_pos_size = 64;
+                rdev->config.evergreen.sx_max_export_smx_size = 192;
+                rdev->config.evergreen.max_hw_contexts = 8;
+                rdev->config.evergreen.sq_num_cf_insts = 2;
+
+                rdev->config.evergreen.sc_prim_fifo_size = 0x40;
+                rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
+                rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                break;
+        case CHIP_SUMO2:
+                rdev->config.evergreen.num_ses = 1;
+                rdev->config.evergreen.max_pipes = 4;
+                rdev->config.evergreen.max_tile_pipes = 4;
+                rdev->config.evergreen.max_simds = 2;
+                rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
+                rdev->config.evergreen.max_gprs = 256;
+                rdev->config.evergreen.max_threads = 248;
+                rdev->config.evergreen.max_gs_threads = 32;
+                rdev->config.evergreen.max_stack_entries = 512;
+                rdev->config.evergreen.sx_num_of_sets = 4;
+                rdev->config.evergreen.sx_max_export_size = 256;
+                rdev->config.evergreen.sx_max_export_pos_size = 64;
+                rdev->config.evergreen.sx_max_export_smx_size = 192;
+                rdev->config.evergreen.max_hw_contexts = 8;
+                rdev->config.evergreen.sq_num_cf_insts = 2;
+
+                rdev->config.evergreen.sc_prim_fifo_size = 0x40;
+                rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
+                rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                break;
         case CHIP_BARTS:
                 rdev->config.evergreen.num_ses = 2;
                 rdev->config.evergreen.max_pipes = 4;
@@ -2054,6 +2106,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         switch (rdev->family) {
         case CHIP_CEDAR:
         case CHIP_PALM:
+        case CHIP_SUMO:
+        case CHIP_SUMO2:
         case CHIP_CAICOS:
                 /* no vertex cache */
                 sq_config &= ~VC_ENABLE;
@@ -2075,6 +2129,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         switch (rdev->family) {
         case CHIP_CEDAR:
         case CHIP_PALM:
+        case CHIP_SUMO:
+        case CHIP_SUMO2:
                 ps_thread_count = 96;
                 break;
         default:
@@ -2114,6 +2170,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         switch (rdev->family) {
         case CHIP_CEDAR:
         case CHIP_PALM:
+        case CHIP_SUMO:
+        case CHIP_SUMO2:
         case CHIP_CAICOS:
                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
                 break;
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index a60ad28b0389..57f3bc17b87e 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -153,6 +153,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 
         if ((rdev->family == CHIP_CEDAR) ||
             (rdev->family == CHIP_PALM) ||
+            (rdev->family == CHIP_SUMO) ||
+            (rdev->family == CHIP_SUMO2) ||
             (rdev->family == CHIP_CAICOS))
                 cp_set_surface_sync(rdev,
                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
@@ -379,6 +381,48 @@ set_default_state(struct radeon_device *rdev)
                         num_hs_stack_entries = 42;
                         num_ls_stack_entries = 42;
                         break;
+                case CHIP_SUMO:
+                        num_ps_gprs = 93;
+                        num_vs_gprs = 46;
+                        num_temp_gprs = 4;
+                        num_gs_gprs = 31;
+                        num_es_gprs = 31;
+                        num_hs_gprs = 23;
+                        num_ls_gprs = 23;
+                        num_ps_threads = 96;
+                        num_vs_threads = 25;
+                        num_gs_threads = 25;
+                        num_es_threads = 25;
+                        num_hs_threads = 25;
+                        num_ls_threads = 25;
+                        num_ps_stack_entries = 42;
+                        num_vs_stack_entries = 42;
+                        num_gs_stack_entries = 42;
+                        num_es_stack_entries = 42;
+                        num_hs_stack_entries = 42;
+                        num_ls_stack_entries = 42;
+                        break;
+                case CHIP_SUMO2:
+                        num_ps_gprs = 93;
+                        num_vs_gprs = 46;
+                        num_temp_gprs = 4;
+                        num_gs_gprs = 31;
+                        num_es_gprs = 31;
+                        num_hs_gprs = 23;
+                        num_ls_gprs = 23;
+                        num_ps_threads = 96;
+                        num_vs_threads = 25;
+                        num_gs_threads = 25;
+                        num_es_threads = 25;
+                        num_hs_threads = 25;
+                        num_ls_threads = 25;
+                        num_ps_stack_entries = 85;
+                        num_vs_stack_entries = 85;
+                        num_gs_stack_entries = 85;
+                        num_es_stack_entries = 85;
+                        num_hs_stack_entries = 85;
+                        num_ls_stack_entries = 85;
+                        break;
                 case CHIP_BARTS:
                         num_ps_gprs = 93;
                         num_vs_gprs = 46;
@@ -446,6 +490,8 @@ set_default_state(struct radeon_device *rdev)
 
                 if ((rdev->family == CHIP_CEDAR) ||
                     (rdev->family == CHIP_PALM) ||
+                    (rdev->family == CHIP_SUMO) ||
+                    (rdev->family == CHIP_SUMO2) ||
                     (rdev->family == CHIP_CAICOS))
                         sq_config = 0;
                 else
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6f27593901c7..d74d4d71437f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -87,6 +87,10 @@ MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
 MODULE_FIRMWARE("radeon/PALM_me.bin");
 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
+MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
+MODULE_FIRMWARE("radeon/SUMO_me.bin");
+MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
+MODULE_FIRMWARE("radeon/SUMO2_me.bin");
 
 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 
@@ -2024,6 +2028,14 @@ int r600_init_microcode(struct radeon_device *rdev)
                 chip_name = "PALM";
                 rlc_chip_name = "SUMO";
                 break;
+        case CHIP_SUMO:
+                chip_name = "SUMO";
+                rlc_chip_name = "SUMO";
+                break;
+        case CHIP_SUMO2:
+                chip_name = "SUMO2";
+                rlc_chip_name = "SUMO";
+                break;
         default: BUG();
         }