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authorDave Airlie <airlied@redhat.com>2014-08-25 19:04:32 -0400
committerDave Airlie <airlied@redhat.com>2014-08-25 19:04:32 -0400
commitd5a0f2e7be20d29c5a23fdbc65c1f8307690413c (patch)
tree1f56a52a35825a209aa26986852b45b9e3fddf29
parentc0ee755fc57319a623e0d9ef839cf8fb26ce8d60 (diff)
parent2c0827cffca8ac0c654b888c58a1989a5172f007 (diff)
Merge tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel into drm-next
- Setting dp M2/N2 values plus state checker support (Vandana Kannan) - chv power well support (Ville) - DP training pattern 3 support for chv (Ville) - cleanup of the hsw/bdw ddi pll code, prep work for skl (Damien) - dsi video burst mode support (Shobhit) - piles of other chv fixes all over (Ville et. al.) - cleanup of the ddi translation tables setup code (Damien) - 180 deg rotation support (Ville & Sonika Jindal) * tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel: (59 commits) drm/i915: Update DRIVER_DATE to 20140808 drm/i915: No busy-loop wait_for in the ring init code drm/i915: Add sprite watermark programming for VLV and CHV drm/i915: Round-up clock and limit drain latency drm/i915: Generalize drain latency computation drm/i915: Free pending page flip events at .preclose() drm/i915: clean up PPGTT checking logic drm/i915: Polish the chv cmnlane resrt macros drm/i915: Hack to tie both common lanes together on chv drm/i915: Add cherryview_update_wm() drm/i915: Update DDL only for current CRTC drm/i915: Parametrize VLV_DDL registers drm/i915: Fill out the FWx watermark register defines drm: Resetting rotation property drm/i915: Add rotation property for sprites drm: Add rotation_property to mode_config drm/i915: Make intel_plane_restore() return an error drm/i915: Add 180 degree sprite rotation support drm/i915: Introduce a for_each_intel_encoder() macro drm/i915: Demote the DRRS messages to debug messages ...
Diffstat
-rw-r--r--Documentation/DocBook/drm.tmpl1
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c9
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c45
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c3
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h22
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c11
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.h1
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c15
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h234
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c13
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h3
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c171
-rw-r--r--drivers/gpu/drm/i915/intel_display.c340
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c50
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h9
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.c40
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.h2
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_cmd.c2
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_panel_vbt.c38
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_pll.c17
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c8
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c3
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c528
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c4
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c98
-rw-r--r--include/drm/drmP.h11
-rw-r--r--include/drm/drm_crtc.h1
27 files changed, 1281 insertions, 398 deletions
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index bacefc5b222e..5c299fa4e016 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -3400,6 +3400,7 @@ void (*disable_vblank) (struct drm_device *dev, int crtc);</synopsis>
3400 <sect2> 3400 <sect2>
3401 <title>Vertical Blanking and Interrupt Handling Functions Reference</title> 3401 <title>Vertical Blanking and Interrupt Handling Functions Reference</title>
3402!Edrivers/gpu/drm/drm_irq.c 3402!Edrivers/gpu/drm/drm_irq.c
3403!Iinclude/drm/drmP.h drm_crtc_vblank_waitqueue
3403 </sect2> 3404 </sect2>
3404 </sect1> 3405 </sect1>
3405 3406
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 6019392b19cc..63d7b8eb6c17 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -291,10 +291,17 @@ static bool restore_fbdev_mode(struct drm_fb_helper *fb_helper)
291 291
292 drm_warn_on_modeset_not_all_locked(dev); 292 drm_warn_on_modeset_not_all_locked(dev);
293 293
294 list_for_each_entry(plane, &dev->mode_config.plane_list, head) 294 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
295 if (plane->type != DRM_PLANE_TYPE_PRIMARY) 295 if (plane->type != DRM_PLANE_TYPE_PRIMARY)
296 drm_plane_force_disable(plane); 296 drm_plane_force_disable(plane);
297 297
298 if (dev->mode_config.rotation_property) {
299 drm_object_property_set_value(&plane->base,
300 dev->mode_config.rotation_property,
301 BIT(DRM_ROTATE_0));
302 }
303 }
304
298 for (i = 0; i < fb_helper->crtc_count; i++) { 305 for (i = 0; i < fb_helper->crtc_count; i++) {
299 struct drm_mode_set *mode_set = &fb_helper->crtc_info[i].mode_set; 306 struct drm_mode_set *mode_set = &fb_helper->crtc_info[i].mode_set;
300 struct drm_crtc *crtc = mode_set->crtc; 307 struct drm_crtc *crtc = mode_set->crtc;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9e737b771c40..330caa1ab9f9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
1433 return 0; 1433 return 0;
1434} 1434}
1435 1435
1436static int i915_fbc_fc_get(void *data, u64 *val)
1437{
1438 struct drm_device *dev = data;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1440
1441 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1442 return -ENODEV;
1443
1444 drm_modeset_lock_all(dev);
1445 *val = dev_priv->fbc.false_color;
1446 drm_modeset_unlock_all(dev);
1447
1448 return 0;
1449}
1450
1451static int i915_fbc_fc_set(void *data, u64 val)
1452{
1453 struct drm_device *dev = data;
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 u32 reg;
1456
1457 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1458 return -ENODEV;
1459
1460 drm_modeset_lock_all(dev);
1461
1462 reg = I915_READ(ILK_DPFC_CONTROL);
1463 dev_priv->fbc.false_color = val;
1464
1465 I915_WRITE(ILK_DPFC_CONTROL, val ?
1466 (reg | FBC_CTL_FALSE_COLOR) :
1467 (reg & ~FBC_CTL_FALSE_COLOR));
1468
1469 drm_modeset_unlock_all(dev);
1470 return 0;
1471}
1472
1473DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1474 i915_fbc_fc_get, i915_fbc_fc_set,
1475 "%llu\n");
1476
1436static int i915_ips_status(struct seq_file *m, void *unused) 1477static int i915_ips_status(struct seq_file *m, void *unused)
1437{ 1478{
1438 struct drm_info_node *node = m->private; 1479 struct drm_info_node *node = m->private;
@@ -2667,8 +2708,7 @@ static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2667 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 2708 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2668 2709
2669 drm_modeset_lock_all(dev); 2710 drm_modeset_lock_all(dev);
2670 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 2711 for_each_intel_encoder(dev, encoder) {
2671 base.head) {
2672 if (!encoder->base.crtc) 2712 if (!encoder->base.crtc)
2673 continue; 2713 continue;
2674 2714
@@ -3957,6 +3997,7 @@ static const struct i915_debugfs_files {
3957 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, 3997 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3958 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, 3998 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3959 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, 3999 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4000 {"i915_fbc_false_color", &i915_fbc_fc_fops},
3960}; 4001};
3961 4002
3962void intel_display_crc_init(struct drm_device *dev) 4003void intel_display_crc_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2e7f03ad5ee2..c965698a8bac 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1981,6 +1981,9 @@ void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1981 i915_gem_context_close(dev, file); 1981 i915_gem_context_close(dev, file);
1982 i915_gem_release(dev, file); 1982 i915_gem_release(dev, file);
1983 mutex_unlock(&dev->struct_mutex); 1983 mutex_unlock(&dev->struct_mutex);
1984
1985 if (drm_core_check_feature(dev, DRIVER_MODESET))
1986 intel_modeset_preclose(dev, file);
1984} 1987}
1985 1988
1986void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1989void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a830eac5ba3..0730af32afe6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,7 +53,7 @@
53 53
54#define DRIVER_NAME "i915" 54#define DRIVER_NAME "i915"
55#define DRIVER_DESC "Intel Graphics" 55#define DRIVER_DESC "Intel Graphics"
56#define DRIVER_DATE "20140725" 56#define DRIVER_DATE "20140808"
57 57
58enum pipe { 58enum pipe {
59 INVALID_PIPE = -1, 59 INVALID_PIPE = -1,
@@ -171,6 +171,11 @@ enum hpd_pin {
171#define for_each_intel_crtc(dev, intel_crtc) \ 171#define for_each_intel_crtc(dev, intel_crtc) \
172 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 172 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
173 173
174#define for_each_intel_encoder(dev, intel_encoder) \
175 list_for_each_entry(intel_encoder, \
176 &(dev)->mode_config.encoder_list, \
177 base.head)
178
174#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 179#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
175 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 180 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
176 if ((intel_encoder)->base.crtc == (__crtc)) 181 if ((intel_encoder)->base.crtc == (__crtc))
@@ -197,10 +202,13 @@ enum intel_dpll_id {
197#define I915_NUM_PLLS 2 202#define I915_NUM_PLLS 2
198 203
199struct intel_dpll_hw_state { 204struct intel_dpll_hw_state {
205 /* i9xx, pch plls */
200 uint32_t dpll; 206 uint32_t dpll;
201 uint32_t dpll_md; 207 uint32_t dpll_md;
202 uint32_t fp0; 208 uint32_t fp0;
203 uint32_t fp1; 209 uint32_t fp1;
210
211 /* hsw, bdw */
204 uint32_t wrpll; 212 uint32_t wrpll;
205}; 213};
206 214
@@ -634,6 +642,8 @@ struct i915_fbc {
634 struct drm_mm_node compressed_fb; 642 struct drm_mm_node compressed_fb;
635 struct drm_mm_node *compressed_llb; 643 struct drm_mm_node *compressed_llb;
636 644
645 bool false_color;
646
637 struct intel_fbc_work { 647 struct intel_fbc_work {
638 struct delayed_work work; 648 struct delayed_work work;
639 struct drm_crtc *crtc; 649 struct drm_crtc *crtc;
@@ -1227,6 +1237,12 @@ enum modeset_restore {
1227}; 1237};
1228 1238
1229struct ddi_vbt_port_info { 1239struct ddi_vbt_port_info {
1240 /*
1241 * This is an index in the HDMI/DVI DDI buffer translation table.
1242 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1243 * populate this field.
1244 */
1245#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1230 uint8_t hdmi_level_shift; 1246 uint8_t hdmi_level_shift;
1231 1247
1232 uint8_t supports_dvi:1; 1248 uint8_t supports_dvi:1;
@@ -2049,8 +2065,8 @@ struct drm_i915_cmd_table {
2049#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 2065#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2050#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6) 2066#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2051#define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev)) 2067#define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2052#define USES_PPGTT(dev) intel_enable_ppgtt(dev, false) 2068#define USES_PPGTT(dev) (i915.enable_ppgtt)
2053#define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true) 2069#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2054 2070
2055#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2071#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2056#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2072#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1411613f2174..b4b7cfd226b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -33,17 +33,6 @@
33static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); 33static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
34static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); 34static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
35 35
36bool intel_enable_ppgtt(struct drm_device *dev, bool full)
37{
38 if (i915.enable_ppgtt == 0)
39 return false;
40
41 if (i915.enable_ppgtt == 1 && full)
42 return false;
43
44 return true;
45}
46
47static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) 36static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
48{ 37{
49 if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) 38 if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8d6f7c18c404..666c938a51e3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -272,7 +272,6 @@ void i915_gem_init_global_gtt(struct drm_device *dev);
272void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, 272void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
273 unsigned long mappable_end, unsigned long end); 273 unsigned long mappable_end, unsigned long end);
274 274
275bool intel_enable_ppgtt(struct drm_device *dev, bool full);
276int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 275int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
277 276
278void i915_check_and_clear_faults(struct drm_device *dev); 277void i915_check_and_clear_faults(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0050ee9470f1..7ccc900eaf6b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -151,7 +151,7 @@ ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
151{ 151{
152 assert_spin_locked(&dev_priv->irq_lock); 152 assert_spin_locked(&dev_priv->irq_lock);
153 153
154 if (!intel_irqs_enabled(dev_priv)) 154 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
155 return; 155 return;
156 156
157 if ((dev_priv->irq_mask & mask) != mask) { 157 if ((dev_priv->irq_mask & mask) != mask) {
@@ -1984,14 +1984,9 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1984 1984
1985static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) 1985static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1986{ 1986{
1987 struct intel_crtc *crtc;
1988
1989 if (!drm_handle_vblank(dev, pipe)) 1987 if (!drm_handle_vblank(dev, pipe))
1990 return false; 1988 return false;
1991 1989
1992 crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1993 wake_up(&crtc->vbl_wait);
1994
1995 return true; 1990 return true;
1996} 1991}
1997 1992
@@ -3522,18 +3517,17 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
3522static void ibx_hpd_irq_setup(struct drm_device *dev) 3517static void ibx_hpd_irq_setup(struct drm_device *dev)
3523{ 3518{
3524 struct drm_i915_private *dev_priv = dev->dev_private; 3519 struct drm_i915_private *dev_priv = dev->dev_private;
3525 struct drm_mode_config *mode_config = &dev->mode_config;
3526 struct intel_encoder *intel_encoder; 3520 struct intel_encoder *intel_encoder;
3527 u32 hotplug_irqs, hotplug, enabled_irqs = 0; 3521 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3528 3522
3529 if (HAS_PCH_IBX(dev)) { 3523 if (HAS_PCH_IBX(dev)) {
3530 hotplug_irqs = SDE_HOTPLUG_MASK; 3524 hotplug_irqs = SDE_HOTPLUG_MASK;
3531 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 3525 for_each_intel_encoder(dev, intel_encoder)
3532 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 3526 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3533 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; 3527 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3534 } else { 3528 } else {
3535 hotplug_irqs = SDE_HOTPLUG_MASK_CPT; 3529 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3536 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 3530 for_each_intel_encoder(dev, intel_encoder)
3537 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 3531 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3538 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; 3532 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3539 } 3533 }
@@ -4444,7 +4438,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
4444static void i915_hpd_irq_setup(struct drm_device *dev) 4438static void i915_hpd_irq_setup(struct drm_device *dev)
4445{ 4439{
4446 struct drm_i915_private *dev_priv = dev->dev_private; 4440 struct drm_i915_private *dev_priv = dev->dev_private;
4447 struct drm_mode_config *mode_config = &dev->mode_config;
4448 struct intel_encoder *intel_encoder; 4441 struct intel_encoder *intel_encoder;
4449 u32 hotplug_en; 4442 u32 hotplug_en;
4450 4443
@@ -4455,7 +4448,7 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
4455 hotplug_en &= ~HOTPLUG_INT_EN_MASK; 4448 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4456 /* Note HDMI and DP share hotplug bits */ 4449 /* Note HDMI and DP share hotplug bits */
4457 /* enable bits are the same for all generations */ 4450 /* enable bits are the same for all generations */
4458 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 4451 for_each_intel_encoder(dev, intel_encoder)
4459 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 4452 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4460 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; 4453 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4461 /* Programming the CRT detection parameters tends 4454 /* Programming the CRT detection parameters tends
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e4d7607da2c4..7a6cc69cdc2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -497,10 +497,26 @@
497#define BUNIT_REG_BISOC 0x11 497#define BUNIT_REG_BISOC 0x11
498 498
499#define PUNIT_REG_DSPFREQ 0x36 499#define PUNIT_REG_DSPFREQ 0x36
500#define DSPFREQSTAT_SHIFT_CHV 24
501#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
502#define DSPFREQGUAR_SHIFT_CHV 8
503#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
500#define DSPFREQSTAT_SHIFT 30 504#define DSPFREQSTAT_SHIFT 30
501#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 505#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
502#define DSPFREQGUAR_SHIFT 14 506#define DSPFREQGUAR_SHIFT 14
503#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 507#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
508#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
509#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
510#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
511#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
512#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
513#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
514#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
515#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
516#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
517#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
518#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
519#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
504 520
505/* See the PUNIT HAS v0.8 for the below bits */ 521/* See the PUNIT HAS v0.8 for the below bits */
506enum punit_power_well { 522enum punit_power_well {
@@ -514,6 +530,11 @@ enum punit_power_well {
514 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 530 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
515 PUNIT_POWER_WELL_DPIO_RX0 = 10, 531 PUNIT_POWER_WELL_DPIO_RX0 = 10,
516 PUNIT_POWER_WELL_DPIO_RX1 = 11, 532 PUNIT_POWER_WELL_DPIO_RX1 = 11,
533 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
534 /* FIXME: guesswork below */
535 PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13,
536 PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14,
537 PUNIT_POWER_WELL_DPIO_RX2 = 15,
517 538
518 PUNIT_POWER_WELL_NUM, 539 PUNIT_POWER_WELL_NUM,
519}; 540};
@@ -834,8 +855,8 @@ enum punit_power_well {
834 855
835#define _VLV_TX_DW2_CH0 0x8288 856#define _VLV_TX_DW2_CH0 0x8288
836#define _VLV_TX_DW2_CH1 0x8488 857#define _VLV_TX_DW2_CH1 0x8488
837#define DPIO_SWING_MARGIN_SHIFT 16 858#define DPIO_SWING_MARGIN000_SHIFT 16
838#define DPIO_SWING_MARGIN_MASK (0xff << DPIO_SWING_MARGIN_SHIFT) 859#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
839#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 860#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
840#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 861#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
841 862
@@ -843,12 +864,16 @@ enum punit_power_well {
843#define _VLV_TX_DW3_CH1 0x848c 864#define _VLV_TX_DW3_CH1 0x848c
844/* The following bit for CHV phy */ 865/* The following bit for CHV phy */
845#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 866#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
867#define DPIO_SWING_MARGIN101_SHIFT 16
868#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
846#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 869#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
847 870
848#define _VLV_TX_DW4_CH0 0x8290 871#define _VLV_TX_DW4_CH0 0x8290
849#define _VLV_TX_DW4_CH1 0x8490 872#define _VLV_TX_DW4_CH1 0x8490
850#define DPIO_SWING_DEEMPH9P5_SHIFT 24 873#define DPIO_SWING_DEEMPH9P5_SHIFT 24
851#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 874#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
875#define DPIO_SWING_DEEMPH6P0_SHIFT 16
876#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
852#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 877#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
853 878
854#define _VLV_TX3_DW4_CH0 0x690 879#define _VLV_TX3_DW4_CH0 0x690
@@ -1515,6 +1540,7 @@ enum punit_power_well {
1515/* Framebuffer compression for Ironlake */ 1540/* Framebuffer compression for Ironlake */
1516#define ILK_DPFC_CB_BASE 0x43200 1541#define ILK_DPFC_CB_BASE 0x43200
1517#define ILK_DPFC_CONTROL 0x43208 1542#define ILK_DPFC_CONTROL 0x43208
1543#define FBC_CTL_FALSE_COLOR (1<<10)
1518/* The bit 28-8 is reserved */ 1544/* The bit 28-8 is reserved */
1519#define DPFC_RESERVED (0x1FFFFF00) 1545#define DPFC_RESERVED (0x1FFFFF00)
1520#define ILK_DPFC_RECOMP_CTL 0x4320c 1546#define ILK_DPFC_RECOMP_CTL 0x4320c
@@ -1671,12 +1697,9 @@ enum punit_power_well {
1671#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) 1697#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
1672#define DPLL_PORTD_READY_MASK (0xf) 1698#define DPLL_PORTD_READY_MASK (0xf)
1673#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) 1699#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
1674#define PHY_COM_LANE_RESET_DEASSERT(phy, val) \ 1700#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
1675 ((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
1676#define PHY_COM_LANE_RESET_ASSERT(phy, val) \
1677 ((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
1678#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) 1701#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
1679#define PHY_POWERGOOD(phy) ((phy == DPIO_PHY0) ? (1<<31) : (1<<30)) 1702#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
1680 1703
1681/* 1704/*
1682 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1705 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
@@ -3472,6 +3495,8 @@ enum punit_power_well {
3472#define DP_LINK_TRAIN_OFF (3 << 28) 3495#define DP_LINK_TRAIN_OFF (3 << 28)
3473#define DP_LINK_TRAIN_MASK (3 << 28) 3496#define DP_LINK_TRAIN_MASK (3 << 28)
3474#define DP_LINK_TRAIN_SHIFT 28 3497#define DP_LINK_TRAIN_SHIFT 28
3498#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
3499#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
3475 3500
3476/* CPT Link training mode */ 3501/* CPT Link training mode */
3477#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3502#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
@@ -3728,7 +3753,6 @@ enum punit_power_well {
3728#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 3753#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3729#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 3754#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3730#define PIPE_DPST_EVENT_STATUS (1UL<<7) 3755#define PIPE_DPST_EVENT_STATUS (1UL<<7)
3731#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3732#define PIPE_A_PSR_STATUS_VLV (1UL<<6) 3756#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
3733#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 3757#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3734#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 3758#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
@@ -3838,73 +3862,151 @@ enum punit_power_well {
3838#define DSPARB_BEND_SHIFT 9 /* on 855 */ 3862#define DSPARB_BEND_SHIFT 9 /* on 855 */
3839#define DSPARB_AEND_SHIFT 0 3863#define DSPARB_AEND_SHIFT 0
3840 3864
3865/* pnv/gen4/g4x/vlv/chv */
3841#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) 3866#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
3842#define DSPFW_SR_SHIFT 23 3867#define DSPFW_SR_SHIFT 23
3843#define DSPFW_SR_MASK (0x1ff<<23) 3868#define DSPFW_SR_MASK (0x1ff<<23)
3844#define DSPFW_CURSORB_SHIFT 16 3869#define DSPFW_CURSORB_SHIFT 16
3845#define DSPFW_CURSORB_MASK (0x3f<<16) 3870#define DSPFW_CURSORB_MASK (0x3f<<16)
3846#define DSPFW_PLANEB_SHIFT 8 3871#define DSPFW_PLANEB_SHIFT 8
3847#define DSPFW_PLANEB_MASK (0x7f<<8) 3872#define DSPFW_PLANEB_MASK (0x7f<<8)
3848#define DSPFW_PLANEA_MASK (0x7f) 3873#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
3874#define DSPFW_PLANEA_SHIFT 0
3875#define DSPFW_PLANEA_MASK (0x7f<<0)
3876#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
3849#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) 3877#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
3850#define DSPFW_CURSORA_MASK 0x00003f00 3878#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
3851#define DSPFW_CURSORA_SHIFT 8 3879#define DSPFW_FBC_SR_SHIFT 28
3852#define DSPFW_PLANEC_MASK (0x7f) 3880#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
3881#define DSPFW_FBC_HPLL_SR_SHIFT 24
3882#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
3883#define DSPFW_SPRITEB_SHIFT (16)
3884#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
3885#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
3886#define DSPFW_CURSORA_SHIFT 8
3887#define DSPFW_CURSORA_MASK (0x3f<<8)
3888#define DSPFW_PLANEC_SHIFT_OLD 0
3889#define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */
3890#define DSPFW_SPRITEA_SHIFT 0
3891#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
3892#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
3853#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) 3893#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
3854#define DSPFW_HPLL_SR_EN (1<<31) 3894#define DSPFW_HPLL_SR_EN (1<<31)
3855#define DSPFW_CURSOR_SR_SHIFT 24
3856#define PINEVIEW_SELF_REFRESH_EN (1<<30) 3895#define PINEVIEW_SELF_REFRESH_EN (1<<30)
3896#define DSPFW_CURSOR_SR_SHIFT 24
3857#define DSPFW_CURSOR_SR_MASK (0x3f<<24) 3897#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3858#define DSPFW_HPLL_CURSOR_SHIFT 16 3898#define DSPFW_HPLL_CURSOR_SHIFT 16
3859#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 3899#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3860#define DSPFW_HPLL_SR_MASK (0x1ff) 3900#define DSPFW_HPLL_SR_SHIFT 0
3861#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070) 3901#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
3862#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c) 3902
3903/* vlv/chv */
3904#define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
3905#define DSPFW_SPRITEB_WM1_SHIFT 16
3906#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
3907#define DSPFW_CURSORA_WM1_SHIFT 8
3908#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
3909#define DSPFW_SPRITEA_WM1_SHIFT 0
3910#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
3911#define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
3912#define DSPFW_PLANEB_WM1_SHIFT 24
3913#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
3914#define DSPFW_PLANEA_WM1_SHIFT 16
3915#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
3916#define DSPFW_CURSORB_WM1_SHIFT 8
3917#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
3918#define DSPFW_CURSOR_SR_WM1_SHIFT 0
3919#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
3920#define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
3921#define DSPFW_SR_WM1_SHIFT 0
3922#define DSPFW_SR_WM1_MASK (0x1ff<<0)
3923#define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
3924#define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
3925#define DSPFW_SPRITED_WM1_SHIFT 24
3926#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
3927#define DSPFW_SPRITED_SHIFT 16
3928#define DSPFW_SPRITED_MASK (0xff<<16)
3929#define DSPFW_SPRITEC_WM1_SHIFT 8
3930#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
3931#define DSPFW_SPRITEC_SHIFT 0
3932#define DSPFW_SPRITEC_MASK (0xff<<0)
3933#define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
3934#define DSPFW_SPRITEF_WM1_SHIFT 24
3935#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
3936#define DSPFW_SPRITEF_SHIFT 16
3937#define DSPFW_SPRITEF_MASK (0xff<<16)
3938#define DSPFW_SPRITEE_WM1_SHIFT 8
3939#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
3940#define DSPFW_SPRITEE_SHIFT 0
3941#define DSPFW_SPRITEE_MASK (0xff<<0)
3942#define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
3943#define DSPFW_PLANEC_WM1_SHIFT 24
3944#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
3945#define DSPFW_PLANEC_SHIFT 16
3946#define DSPFW_PLANEC_MASK (0xff<<16)
3947#define DSPFW_CURSORC_WM1_SHIFT 8
3948#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
3949#define DSPFW_CURSORC_SHIFT 0
3950#define DSPFW_CURSORC_MASK (0x3f<<0)
3951
3952/* vlv/chv high order bits */
3953#define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
3954#define DSPFW_SR_HI_SHIFT 24
3955#define DSPFW_SR_HI_MASK (1<<24)
3956#define DSPFW_SPRITEF_HI_SHIFT 23
3957#define DSPFW_SPRITEF_HI_MASK (1<<23)
3958#define DSPFW_SPRITEE_HI_SHIFT 22
3959#define DSPFW_SPRITEE_HI_MASK (1<<22)
3960#define DSPFW_PLANEC_HI_SHIFT 21
3961#define DSPFW_PLANEC_HI_MASK (1<<21)
3962#define DSPFW_SPRITED_HI_SHIFT 20
3963#define DSPFW_SPRITED_HI_MASK (1<<20)
3964#define DSPFW_SPRITEC_HI_SHIFT 16
3965#define DSPFW_SPRITEC_HI_MASK (1<<16)
3966#define DSPFW_PLANEB_HI_SHIFT 12
3967#define DSPFW_PLANEB_HI_MASK (1<<12)
3968#define DSPFW_SPRITEB_HI_SHIFT 8
3969#define DSPFW_SPRITEB_HI_MASK (1<<8)
3970#define DSPFW_SPRITEA_HI_SHIFT 4
3971#define DSPFW_SPRITEA_HI_MASK (1<<4)
3972#define DSPFW_PLANEA_HI_SHIFT 0
3973#define DSPFW_PLANEA_HI_MASK (1<<0)
3974#define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
3975#define DSPFW_SR_WM1_HI_SHIFT 24
3976#define DSPFW_SR_WM1_HI_MASK (1<<24)
3977#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
3978#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
3979#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
3980#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
3981#define DSPFW_PLANEC_WM1_HI_SHIFT 21
3982#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
3983#define DSPFW_SPRITED_WM1_HI_SHIFT 20
3984#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
3985#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
3986#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
3987#define DSPFW_PLANEB_WM1_HI_SHIFT 12
3988#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
3989#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
3990#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
3991#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
3992#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
3993#define DSPFW_PLANEA_WM1_HI_SHIFT 0
3994#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
3863 3995
3864/* drain latency register values*/ 3996/* drain latency register values*/
3865#define DRAIN_LATENCY_PRECISION_32 32 3997#define DRAIN_LATENCY_PRECISION_32 32
3866#define DRAIN_LATENCY_PRECISION_64 64 3998#define DRAIN_LATENCY_PRECISION_64 64
3867#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) 3999#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
3868#define DDL_CURSORA_PRECISION_64 (1<<31) 4000#define DDL_CURSOR_PRECISION_64 (1<<31)
3869#define DDL_CURSORA_PRECISION_32 (0<<31) 4001#define DDL_CURSOR_PRECISION_32 (0<<31)
3870#define DDL_CURSORA_SHIFT 24 4002#define DDL_CURSOR_SHIFT 24
3871#define DDL_SPRITEB_PRECISION_64 (1<<23) 4003#define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite)))
3872#define DDL_SPRITEB_PRECISION_32 (0<<23) 4004#define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite)))
3873#define DDL_SPRITEB_SHIFT 16 4005#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
3874#define DDL_SPRITEA_PRECISION_64 (1<<15) 4006#define DDL_PLANE_PRECISION_64 (1<<7)
3875#define DDL_SPRITEA_PRECISION_32 (0<<15) 4007#define DDL_PLANE_PRECISION_32 (0<<7)
3876#define DDL_SPRITEA_SHIFT 8 4008#define DDL_PLANE_SHIFT 0
3877#define DDL_PLANEA_PRECISION_64 (1<<7) 4009#define DRAIN_LATENCY_MASK 0x7f
3878#define DDL_PLANEA_PRECISION_32 (0<<7)
3879#define DDL_PLANEA_SHIFT 0
3880
3881#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
3882#define DDL_CURSORB_PRECISION_64 (1<<31)
3883#define DDL_CURSORB_PRECISION_32 (0<<31)
3884#define DDL_CURSORB_SHIFT 24
3885#define DDL_SPRITED_PRECISION_64 (1<<23)
3886#define DDL_SPRITED_PRECISION_32 (0<<23)
3887#define DDL_SPRITED_SHIFT 16
3888#define DDL_SPRITEC_PRECISION_64 (1<<15)
3889#define DDL_SPRITEC_PRECISION_32 (0<<15)
3890#define DDL_SPRITEC_SHIFT 8
3891#define DDL_PLANEB_PRECISION_64 (1<<7)
3892#define DDL_PLANEB_PRECISION_32 (0<<7)
3893#define DDL_PLANEB_SHIFT 0
3894
3895#define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058)
3896#define DDL_CURSORC_PRECISION_64 (1<<31)
3897#define DDL_CURSORC_PRECISION_32 (0<<31)
3898#define DDL_CURSORC_SHIFT 24
3899#define DDL_SPRITEF_PRECISION_64 (1<<23)
3900#define DDL_SPRITEF_PRECISION_32 (0<<23)
3901#define DDL_SPRITEF_SHIFT 16
3902#define DDL_SPRITEE_PRECISION_64 (1<<15)
3903#define DDL_SPRITEE_PRECISION_32 (0<<15)
3904#define DDL_SPRITEE_SHIFT 8
3905#define DDL_PLANEC_PRECISION_64 (1<<7)
3906#define DDL_PLANEC_PRECISION_32 (0<<7)
3907#define DDL_PLANEC_SHIFT 0
3908 4010
3909/* FIFO watermark sizes etc */ 4011/* FIFO watermark sizes etc */
3910#define G4X_FIFO_LINE_SIZE 64 4012#define G4X_FIFO_LINE_SIZE 64
@@ -4191,6 +4293,7 @@ enum punit_power_well {
4191#define DVS_YUV_ORDER_UYVY (1<<16) 4293#define DVS_YUV_ORDER_UYVY (1<<16)
4192#define DVS_YUV_ORDER_YVYU (2<<16) 4294#define DVS_YUV_ORDER_YVYU (2<<16)
4193#define DVS_YUV_ORDER_VYUY (3<<16) 4295#define DVS_YUV_ORDER_VYUY (3<<16)
4296#define DVS_ROTATE_180 (1<<15)
4194#define DVS_DEST_KEY (1<<2) 4297#define DVS_DEST_KEY (1<<2)
4195#define DVS_TRICKLE_FEED_DISABLE (1<<14) 4298#define DVS_TRICKLE_FEED_DISABLE (1<<14)
4196#define DVS_TILED (1<<10) 4299#define DVS_TILED (1<<10)
@@ -4261,6 +4364,7 @@ enum punit_power_well {
4261#define SPRITE_YUV_ORDER_UYVY (1<<16) 4364#define SPRITE_YUV_ORDER_UYVY (1<<16)
4262#define SPRITE_YUV_ORDER_YVYU (2<<16) 4365#define SPRITE_YUV_ORDER_YVYU (2<<16)
4263#define SPRITE_YUV_ORDER_VYUY (3<<16) 4366#define SPRITE_YUV_ORDER_VYUY (3<<16)
4367#define SPRITE_ROTATE_180 (1<<15)
4264#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 4368#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
4265#define SPRITE_INT_GAMMA_ENABLE (1<<13) 4369#define SPRITE_INT_GAMMA_ENABLE (1<<13)
4266#define SPRITE_TILED (1<<10) 4370#define SPRITE_TILED (1<<10)
@@ -4334,6 +4438,7 @@ enum punit_power_well {
4334#define SP_YUV_ORDER_UYVY (1<<16) 4438#define SP_YUV_ORDER_UYVY (1<<16)
4335#define SP_YUV_ORDER_YVYU (2<<16) 4439#define SP_YUV_ORDER_YVYU (2<<16)
4336#define SP_YUV_ORDER_VYUY (3<<16) 4440#define SP_YUV_ORDER_VYUY (3<<16)
4441#define SP_ROTATE_180 (1<<15)
4337#define SP_TILED (1<<10) 4442#define SP_TILED (1<<10)
4338#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4443#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4339#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4444#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
@@ -5403,7 +5508,6 @@ enum punit_power_well {
5403#define VLV_GTLC_ALLOWWAKEERR (1 << 1) 5508#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
5404#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 5509#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
5405#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 5510#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
5406#define VLV_GTLC_SURVIVABILITY_REG 0x130098
5407#define FORCEWAKE_MT 0xa188 /* multi-threaded */ 5511#define FORCEWAKE_MT 0xa188 /* multi-threaded */
5408#define FORCEWAKE_KERNEL 0x1 5512#define FORCEWAKE_KERNEL 0x1
5409#define FORCEWAKE_USER 0x2 5513#define FORCEWAKE_USER 0x2
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index a66955037e4e..031c5657255d 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -976,12 +976,10 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
976 if (bdb->version >= 158) { 976 if (bdb->version >= 158) {
977 /* The VBT HDMI level shift values match the table we have. */ 977 /* The VBT HDMI level shift values match the table we have. */
978 hdmi_level_shift = child->raw[7] & 0xF; 978 hdmi_level_shift = child->raw[7] & 0xF;
979 if (hdmi_level_shift < 0xC) { 979 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
980 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", 980 port_name(port),
981 port_name(port), 981 hdmi_level_shift);
982 hdmi_level_shift); 982 info->hdmi_level_shift = hdmi_level_shift;
983 info->hdmi_level_shift = hdmi_level_shift;
984 }
985 } 983 }
986} 984}
987 985
@@ -1114,8 +1112,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
1114 struct ddi_vbt_port_info *info = 1112 struct ddi_vbt_port_info *info =
1115 &dev_priv->vbt.ddi_port_info[port]; 1113 &dev_priv->vbt.ddi_port_info[port];
1116 1114
1117 /* Recommended BSpec default: 800mV 0dB. */ 1115 info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN;
1118 info->hdmi_level_shift = 6;
1119 1116
1120 info->supports_dvi = (port != PORT_A && port != PORT_E); 1117 info->supports_dvi = (port != PORT_A && port != PORT_E);
1121 info->supports_hdmi = info->supports_dvi; 1118 info->supports_hdmi = info->supports_dvi;
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index b98667796337..905999bee2ac 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -802,7 +802,8 @@ struct mipi_config {
802 802
803 u16 rsvd4; 803 u16 rsvd4;
804 804
805 u8 rsvd5[5]; 805 u8 rsvd5;
806 u32 target_burst_mode_freq;
806 u32 dsi_ddr_clk; 807 u32 dsi_ddr_clk;
807 u32 bridge_ref_clk; 808 u32 bridge_ref_clk;
808 809
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5db0b5552e39..ca1f9a8a7d03 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -33,7 +33,7 @@
33 * automatically adapt to HDMI connections as well 33 * automatically adapt to HDMI connections as well
34 */ 34 */
35static const u32 hsw_ddi_translations_dp[] = { 35static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */ 36 0x00FFFFFF, 0x0006000E,
37 0x00D75FFF, 0x0005000A, 37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006, 38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000, 39 0x80AAAFFF, 0x000B0000,
@@ -45,7 +45,7 @@ static const u32 hsw_ddi_translations_dp[] = {
45}; 45};
46 46
47static const u32 hsw_ddi_translations_fdi[] = { 47static const u32 hsw_ddi_translations_fdi[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */ 48 0x00FFFFFF, 0x0007000E,
49 0x00D75FFF, 0x000F000A, 49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006, 50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000, 51 0x00AAAFFF, 0x001E0000,
@@ -73,7 +73,7 @@ static const u32 hsw_ddi_translations_hdmi[] = {
73}; 73};
74 74
75static const u32 bdw_ddi_translations_edp[] = { 75static const u32 bdw_ddi_translations_edp[] = {
76 0x00FFFFFF, 0x00000012, /* eDP parameters */ 76 0x00FFFFFF, 0x00000012,
77 0x00EBAFFF, 0x00020011, 77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F, 78 0x00C71FFF, 0x0006000F,
79 0x00AAAFFF, 0x000E000A, 79 0x00AAAFFF, 0x000E000A,
@@ -82,11 +82,10 @@ static const u32 bdw_ddi_translations_edp[] = {
82 0x00BEEFFF, 0x000A000C, 82 0x00BEEFFF, 0x000A000C,
83 0x00FFFFFF, 0x0005000F, 83 0x00FFFFFF, 0x0005000F,
84 0x00DB6FFF, 0x000A000C, 84 0x00DB6FFF, 0x000A000C,
85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
86}; 85};
87 86
88static const u32 bdw_ddi_translations_dp[] = { 87static const u32 bdw_ddi_translations_dp[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */ 88 0x00FFFFFF, 0x0007000E,
90 0x00D75FFF, 0x000E000A, 89 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006, 90 0x00BEFFFF, 0x00140006,
92 0x80B2CFFF, 0x001B0002, 91 0x80B2CFFF, 0x001B0002,
@@ -95,11 +94,10 @@ static const u32 bdw_ddi_translations_dp[] = {
95 0x80CB2FFF, 0x001B0002, 94 0x80CB2FFF, 0x001B0002,
96 0x00F7DFFF, 0x00180004, 95 0x00F7DFFF, 0x00180004,
97 0x80D75FFF, 0x001B0002, 96 0x80D75FFF, 0x001B0002,
98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
99}; 97};
100 98
101static const u32 bdw_ddi_translations_fdi[] = { 99static const u32 bdw_ddi_translations_fdi[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */ 100 0x00FFFFFF, 0x0001000E,
103 0x00D75FFF, 0x0004000A, 101 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006, 102 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000, 103 0x00AAAFFF, 0x000C0000,
@@ -108,7 +106,20 @@ static const u32 bdw_ddi_translations_fdi[] = {
108 0x00C30FFF, 0x000C0000, 106 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006, 107 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000, 108 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ 109};
110
111static const u32 bdw_ddi_translations_hdmi[] = {
112 /* Idx NT mV diff T mV diff db */
113 0x00FFFFFF, 0x0007000E, /* 0: 400 400 0 */
114 0x00D75FFF, 0x000E000A, /* 1: 400 600 3.5 */
115 0x00BEFFFF, 0x00140006, /* 2: 400 800 6 */
116 0x00FFFFFF, 0x0009000D, /* 3: 450 450 0 */
117 0x00FFFFFF, 0x000E000A, /* 4: 600 600 0 */
118 0x00D7FFFF, 0x00140006, /* 5: 600 800 2.5 */
119 0x80CB2FFF, 0x001B0002, /* 6: 600 1000 4.5 */
120 0x00FFFFFF, 0x00140006, /* 7: 800 800 0 */
121 0x80E79FFF, 0x001B0002, /* 8: 800 1000 2 */
122 0x80FFFFFF, 0x001B0002, /* 9: 1000 1000 0 */
112}; 123};
113 124
114enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 125enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
@@ -145,26 +156,36 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
145{ 156{
146 struct drm_i915_private *dev_priv = dev->dev_private; 157 struct drm_i915_private *dev_priv = dev->dev_private;
147 u32 reg; 158 u32 reg;
148 int i; 159 int i, n_hdmi_entries, hdmi_800mV_0dB;
149 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 160 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
150 const u32 *ddi_translations_fdi; 161 const u32 *ddi_translations_fdi;
151 const u32 *ddi_translations_dp; 162 const u32 *ddi_translations_dp;
152 const u32 *ddi_translations_edp; 163 const u32 *ddi_translations_edp;
164 const u32 *ddi_translations_hdmi;
153 const u32 *ddi_translations; 165 const u32 *ddi_translations;
154 166
155 if (IS_BROADWELL(dev)) { 167 if (IS_BROADWELL(dev)) {
156 ddi_translations_fdi = bdw_ddi_translations_fdi; 168 ddi_translations_fdi = bdw_ddi_translations_fdi;
157 ddi_translations_dp = bdw_ddi_translations_dp; 169 ddi_translations_dp = bdw_ddi_translations_dp;
158 ddi_translations_edp = bdw_ddi_translations_edp; 170 ddi_translations_edp = bdw_ddi_translations_edp;
171 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
172 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
173 hdmi_800mV_0dB = 7;
159 } else if (IS_HASWELL(dev)) { 174 } else if (IS_HASWELL(dev)) {
160 ddi_translations_fdi = hsw_ddi_translations_fdi; 175 ddi_translations_fdi = hsw_ddi_translations_fdi;
161 ddi_translations_dp = hsw_ddi_translations_dp; 176 ddi_translations_dp = hsw_ddi_translations_dp;
162 ddi_translations_edp = hsw_ddi_translations_dp; 177 ddi_translations_edp = hsw_ddi_translations_dp;
178 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
179 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
180 hdmi_800mV_0dB = 6;
163 } else { 181 } else {
164 WARN(1, "ddi translation table missing\n"); 182 WARN(1, "ddi translation table missing\n");
165 ddi_translations_edp = bdw_ddi_translations_dp; 183 ddi_translations_edp = bdw_ddi_translations_dp;
166 ddi_translations_fdi = bdw_ddi_translations_fdi; 184 ddi_translations_fdi = bdw_ddi_translations_fdi;
167 ddi_translations_dp = bdw_ddi_translations_dp; 185 ddi_translations_dp = bdw_ddi_translations_dp;
186 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
187 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
188 hdmi_800mV_0dB = 7;
168 } 189 }
169 190
170 switch (port) { 191 switch (port) {
@@ -193,9 +214,15 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
193 I915_WRITE(reg, ddi_translations[i]); 214 I915_WRITE(reg, ddi_translations[i]);
194 reg += 4; 215 reg += 4;
195 } 216 }
217
218 /* Choose a good default if VBT is badly populated */
219 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
220 hdmi_level >= n_hdmi_entries)
221 hdmi_level = hdmi_800mV_0dB;
222
196 /* Entry 9 is for HDMI: */ 223 /* Entry 9 is for HDMI: */
197 for (i = 0; i < 2; i++) { 224 for (i = 0; i < 2; i++) {
198 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); 225 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]);
199 reg += 4; 226 reg += 4;
200 } 227 }
201} 228}
@@ -587,8 +614,8 @@ static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
587 return (refclk * n * 100) / (p * r); 614 return (refclk * n * 100) / (p * r);
588} 615}
589 616
590void intel_ddi_clock_get(struct intel_encoder *encoder, 617static void hsw_ddi_clock_get(struct intel_encoder *encoder,
591 struct intel_crtc_config *pipe_config) 618 struct intel_crtc_config *pipe_config)
592{ 619{
593 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 620 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
594 int link_clock = 0; 621 int link_clock = 0;
@@ -643,9 +670,15 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
643 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; 670 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
644} 671}
645 672
673void intel_ddi_clock_get(struct intel_encoder *encoder,
674 struct intel_crtc_config *pipe_config)
675{
676 hsw_ddi_clock_get(encoder, pipe_config);
677}
678
646static void 679static void
647intel_ddi_calculate_wrpll(int clock /* in Hz */, 680hsw_ddi_calculate_wrpll(int clock /* in Hz */,
648 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 681 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
649{ 682{
650 uint64_t freq2k; 683 uint64_t freq2k;
651 unsigned p, n2, r2; 684 unsigned p, n2, r2;
@@ -708,27 +741,17 @@ intel_ddi_calculate_wrpll(int clock /* in Hz */,
708 *r2_out = best.r2; 741 *r2_out = best.r2;
709} 742}
710 743
711/* 744static bool
712 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and 745hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
713 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to 746 struct intel_encoder *intel_encoder,
714 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually 747 int clock)
715 * enable the PLL.
716 */
717bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
718{ 748{
719 struct drm_crtc *crtc = &intel_crtc->base; 749 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
720 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
721 int type = intel_encoder->type;
722 int clock = intel_crtc->config.port_clock;
723
724 intel_put_shared_dpll(intel_crtc);
725
726 if (type == INTEL_OUTPUT_HDMI) {
727 struct intel_shared_dpll *pll; 750 struct intel_shared_dpll *pll;
728 uint32_t val; 751 uint32_t val;
729 unsigned p, n2, r2; 752 unsigned p, n2, r2;
730 753
731 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 754 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
732 755
733 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 756 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
734 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 757 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
@@ -749,6 +772,25 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
749 return true; 772 return true;
750} 773}
751 774
775
776/*
777 * Tries to find a *shared* PLL for the CRTC and store it in
778 * intel_crtc->ddi_pll_sel.
779 *
780 * For private DPLLs, compute_config() should do the selection for us. This
781 * function should be folded into compute_config() eventually.
782 */
783bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
784{
785 struct drm_crtc *crtc = &intel_crtc->base;
786 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
787 int clock = intel_crtc->config.port_clock;
788
789 intel_put_shared_dpll(intel_crtc);
790
791 return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
792}
793
752void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 794void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
753{ 795{
754 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 796 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
@@ -1183,31 +1225,52 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1183 } 1225 }
1184} 1226}
1185 1227
1186int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) 1228static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1229{
1230 uint32_t lcpll = I915_READ(LCPLL_CTL);
1231 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1232
1233 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1234 return 800000;
1235 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1236 return 450000;
1237 else if (freq == LCPLL_CLK_FREQ_450)
1238 return 450000;
1239 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1240 return 540000;
1241 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1242 return 337500;
1243 else
1244 return 675000;
1245}
1246
1247static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1187{ 1248{
1188 struct drm_device *dev = dev_priv->dev; 1249 struct drm_device *dev = dev_priv->dev;
1189 uint32_t lcpll = I915_READ(LCPLL_CTL); 1250 uint32_t lcpll = I915_READ(LCPLL_CTL);
1190 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 1251 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1191 1252
1192 if (lcpll & LCPLL_CD_SOURCE_FCLK) { 1253 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1193 return 800000; 1254 return 800000;
1194 } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) { 1255 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1195 return 450000; 1256 return 450000;
1196 } else if (freq == LCPLL_CLK_FREQ_450) { 1257 else if (freq == LCPLL_CLK_FREQ_450)
1197 return 450000; 1258 return 450000;
1198 } else if (IS_HASWELL(dev)) { 1259 else if (IS_ULT(dev))
1199 if (IS_ULT(dev)) 1260 return 337500;
1200 return 337500; 1261 else
1201 else 1262 return 540000;
1202 return 540000; 1263}
1203 } else { 1264
1204 if (freq == LCPLL_CLK_FREQ_54O_BDW) 1265int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1205 return 540000; 1266{
1206 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 1267 struct drm_device *dev = dev_priv->dev;
1207 return 337500; 1268
1208 else 1269 if (IS_BROADWELL(dev))
1209 return 675000; 1270 return bdw_get_cdclk_freq(dev_priv);
1210 } 1271
1272 /* Haswell */
1273 return hsw_get_cdclk_freq(dev_priv);
1211} 1274}
1212 1275
1213static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, 1276static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
@@ -1248,10 +1311,8 @@ static const char * const hsw_ddi_pll_names[] = {
1248 "WRPLL 2", 1311 "WRPLL 2",
1249}; 1312};
1250 1313
1251void intel_ddi_pll_init(struct drm_device *dev) 1314static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1252{ 1315{
1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254 uint32_t val = I915_READ(LCPLL_CTL);
1255 int i; 1316 int i;
1256 1317
1257 dev_priv->num_shared_dpll = 2; 1318 dev_priv->num_shared_dpll = 2;
@@ -1264,6 +1325,14 @@ void intel_ddi_pll_init(struct drm_device *dev)
1264 dev_priv->shared_dplls[i].get_hw_state = 1325 dev_priv->shared_dplls[i].get_hw_state =
1265 hsw_ddi_pll_get_hw_state; 1326 hsw_ddi_pll_get_hw_state;
1266 } 1327 }
1328}
1329
1330void intel_ddi_pll_init(struct drm_device *dev)
1331{
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 uint32_t val = I915_READ(LCPLL_CTL);
1334
1335 hsw_shared_dplls_init(dev_priv);
1267 1336
1268 /* The LCPLL register should be turned on by the BIOS. For now let's 1337 /* The LCPLL register should be turned on by the BIOS. For now let's
1269 * just check its state and print errors in case something is wrong. 1338 * just check its state and print errors in case something is wrong.
@@ -1444,7 +1513,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
1444 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1513 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1445 } 1514 }
1446 1515
1447 intel_ddi_clock_get(encoder, pipe_config); 1516 hsw_ddi_clock_get(encoder, pipe_config);
1448} 1517}
1449 1518
1450static void intel_ddi_destroy(struct drm_encoder *encoder) 1519static void intel_ddi_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d074d704f458..eab182d960f3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -91,15 +91,16 @@ static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb, 91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd, 92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj); 93 struct drm_i915_gem_object *obj);
94static void intel_dp_set_m_n(struct intel_crtc *crtc);
95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); 95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n); 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99static void ironlake_set_pipeconf(struct drm_crtc *crtc); 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100static void haswell_set_pipeconf(struct drm_crtc *crtc); 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc); 101static void intel_set_pipe_csc(struct drm_crtc *crtc);
102static void vlv_prepare_pll(struct intel_crtc *crtc); 102static void vlv_prepare_pll(struct intel_crtc *crtc);
103static void chv_prepare_pll(struct intel_crtc *crtc);
103 104
104static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) 105static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
105{ 106{
@@ -1513,34 +1514,6 @@ static void intel_init_dpio(struct drm_device *dev)
1513 } 1514 }
1514} 1515}
1515 1516
1516static void intel_reset_dpio(struct drm_device *dev)
1517{
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520 if (IS_CHERRYVIEW(dev)) {
1521 enum dpio_phy phy;
1522 u32 val;
1523
1524 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525 /* Poll for phypwrgood signal */
1526 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527 PHY_POWERGOOD(phy), 1))
1528 DRM_ERROR("Display PHY %d is not power up\n", phy);
1529
1530 /*
1531 * Deassert common lane reset for PHY.
1532 *
1533 * This should only be done on init and resume from S3
1534 * with both PLLs disabled, or we risk losing DPIO and
1535 * PLL synchronization.
1536 */
1537 val = I915_READ(DISPLAY_PHY_CONTROL);
1538 I915_WRITE(DISPLAY_PHY_CONTROL,
1539 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1540 }
1541 }
1542}
1543
1544static void vlv_enable_pll(struct intel_crtc *crtc) 1517static void vlv_enable_pll(struct intel_crtc *crtc)
1545{ 1518{
1546 struct drm_device *dev = crtc->base.dev; 1519 struct drm_device *dev = crtc->base.dev;
@@ -1712,7 +1685,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 assert_pipe_disabled(dev_priv, pipe); 1685 assert_pipe_disabled(dev_priv, pipe);
1713 1686
1714 /* Set PLL en = 0 */ 1687 /* Set PLL en = 0 */
1715 val = DPLL_SSC_REF_CLOCK_CHV; 1688 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1716 if (pipe != PIPE_A) 1689 if (pipe != PIPE_A)
1717 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1690 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1718 I915_WRITE(DPLL(pipe), val); 1691 I915_WRITE(DPLL(pipe), val);
@@ -1806,7 +1779,7 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1806 if (WARN_ON(pll->refcount == 0)) 1779 if (WARN_ON(pll->refcount == 0))
1807 return; 1780 return;
1808 1781
1809 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", 1782 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1810 pll->name, pll->active, pll->on, 1783 pll->name, pll->active, pll->on,
1811 crtc->base.base.id); 1784 crtc->base.base.id);
1812 1785
@@ -3980,7 +3953,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3980 3953
3981 if (intel_crtc->config.has_pch_encoder) { 3954 if (intel_crtc->config.has_pch_encoder) {
3982 intel_cpu_transcoder_set_m_n(intel_crtc, 3955 intel_cpu_transcoder_set_m_n(intel_crtc,
3983 &intel_crtc->config.fdi_m_n); 3956 &intel_crtc->config.fdi_m_n, NULL);
3984 } 3957 }
3985 3958
3986 ironlake_set_pipeconf(crtc); 3959 ironlake_set_pipeconf(crtc);
@@ -4093,7 +4066,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4093 4066
4094 if (intel_crtc->config.has_pch_encoder) { 4067 if (intel_crtc->config.has_pch_encoder) {
4095 intel_cpu_transcoder_set_m_n(intel_crtc, 4068 intel_cpu_transcoder_set_m_n(intel_crtc,
4096 &intel_crtc->config.fdi_m_n); 4069 &intel_crtc->config.fdi_m_n, NULL);
4097 } 4070 }
4098 4071
4099 haswell_set_pipeconf(crtc); 4072 haswell_set_pipeconf(crtc);
@@ -4529,12 +4502,57 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4529 vlv_update_cdclk(dev); 4502 vlv_update_cdclk(dev);
4530} 4503}
4531 4504
4505static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4506{
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 u32 val, cmd;
4509
4510 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4511
4512 switch (cdclk) {
4513 case 400000:
4514 cmd = 3;
4515 break;
4516 case 333333:
4517 case 320000:
4518 cmd = 2;
4519 break;
4520 case 266667:
4521 cmd = 1;
4522 break;
4523 case 200000:
4524 cmd = 0;
4525 break;
4526 default:
4527 WARN_ON(1);
4528 return;
4529 }
4530
4531 mutex_lock(&dev_priv->rps.hw_lock);
4532 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4533 val &= ~DSPFREQGUAR_MASK_CHV;
4534 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4535 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4536 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4537 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4538 50)) {
4539 DRM_ERROR("timed out waiting for CDclk change\n");
4540 }
4541 mutex_unlock(&dev_priv->rps.hw_lock);
4542
4543 vlv_update_cdclk(dev);
4544}
4545
4532static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, 4546static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4533 int max_pixclk) 4547 int max_pixclk)
4534{ 4548{
4535 int vco = valleyview_get_vco(dev_priv); 4549 int vco = valleyview_get_vco(dev_priv);
4536 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; 4550 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4537 4551
4552 /* FIXME: Punit isn't quite ready yet */
4553 if (IS_CHERRYVIEW(dev_priv->dev))
4554 return 400000;
4555
4538 /* 4556 /*
4539 * Really only a few cases to deal with, as only 4 CDclks are supported: 4557 * Really only a few cases to deal with, as only 4 CDclks are supported:
4540 * 200MHz 4558 * 200MHz
@@ -4597,8 +4615,13 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
4597 int max_pixclk = intel_mode_max_pixclk(dev_priv); 4615 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4598 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); 4616 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4599 4617
4600 if (req_cdclk != dev_priv->vlv_cdclk_freq) 4618 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4601 valleyview_set_cdclk(dev, req_cdclk); 4619 if (IS_CHERRYVIEW(dev))
4620 cherryview_set_cdclk(dev, req_cdclk);
4621 else
4622 valleyview_set_cdclk(dev, req_cdclk);
4623 }
4624
4602 modeset_update_crtc_power_domains(dev); 4625 modeset_update_crtc_power_domains(dev);
4603} 4626}
4604 4627
@@ -4620,8 +4643,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
4620 4643
4621 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); 4644 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4622 4645
4623 if (!is_dsi && !IS_CHERRYVIEW(dev)) 4646 if (!is_dsi) {
4624 vlv_prepare_pll(intel_crtc); 4647 if (IS_CHERRYVIEW(dev))
4648 chv_prepare_pll(intel_crtc);
4649 else
4650 vlv_prepare_pll(intel_crtc);
4651 }
4625 4652
4626 /* Set up the display plane register */ 4653 /* Set up the display plane register */
4627 dspcntr = DISPPLANE_GAMMA_ENABLE; 4654 dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -5265,6 +5292,10 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
5265 u32 val; 5292 u32 val;
5266 int divider; 5293 int divider;
5267 5294
5295 /* FIXME: Punit isn't quite ready yet */
5296 if (IS_CHERRYVIEW(dev))
5297 return 400000;
5298
5268 mutex_lock(&dev_priv->dpio_lock); 5299 mutex_lock(&dev_priv->dpio_lock);
5269 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 5300 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5270 mutex_unlock(&dev_priv->dpio_lock); 5301 mutex_unlock(&dev_priv->dpio_lock);
@@ -5509,7 +5540,8 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5509} 5540}
5510 5541
5511static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, 5542static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5512 struct intel_link_m_n *m_n) 5543 struct intel_link_m_n *m_n,
5544 struct intel_link_m_n *m2_n2)
5513{ 5545{
5514 struct drm_device *dev = crtc->base.dev; 5546 struct drm_device *dev = crtc->base.dev;
5515 struct drm_i915_private *dev_priv = dev->dev_private; 5547 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5521,6 +5553,18 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5521 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); 5553 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5522 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); 5554 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5523 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); 5555 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5556 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5557 * for gen < 8) and if DRRS is supported (to make sure the
5558 * registers are not unnecessarily accessed).
5559 */
5560 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5561 crtc->config.has_drrs) {
5562 I915_WRITE(PIPE_DATA_M2(transcoder),
5563 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5564 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5565 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5566 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5567 }
5524 } else { 5568 } else {
5525 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); 5569 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5526 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); 5570 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
@@ -5529,12 +5573,13 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5529 } 5573 }
5530} 5574}
5531 5575
5532static void intel_dp_set_m_n(struct intel_crtc *crtc) 5576void intel_dp_set_m_n(struct intel_crtc *crtc)
5533{ 5577{
5534 if (crtc->config.has_pch_encoder) 5578 if (crtc->config.has_pch_encoder)
5535 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); 5579 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5536 else 5580 else
5537 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); 5581 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5582 &crtc->config.dp_m2_n2);
5538} 5583}
5539 5584
5540static void vlv_update_pll(struct intel_crtc *crtc) 5585static void vlv_update_pll(struct intel_crtc *crtc)
@@ -5652,6 +5697,18 @@ static void vlv_prepare_pll(struct intel_crtc *crtc)
5652 5697
5653static void chv_update_pll(struct intel_crtc *crtc) 5698static void chv_update_pll(struct intel_crtc *crtc)
5654{ 5699{
5700 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5701 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5702 DPLL_VCO_ENABLE;
5703 if (crtc->pipe != PIPE_A)
5704 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5705
5706 crtc->config.dpll_hw_state.dpll_md =
5707 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5708}
5709
5710static void chv_prepare_pll(struct intel_crtc *crtc)
5711{
5655 struct drm_device *dev = crtc->base.dev; 5712 struct drm_device *dev = crtc->base.dev;
5656 struct drm_i915_private *dev_priv = dev->dev_private; 5713 struct drm_i915_private *dev_priv = dev->dev_private;
5657 int pipe = crtc->pipe; 5714 int pipe = crtc->pipe;
@@ -5661,15 +5718,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
5661 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 5718 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5662 int refclk; 5719 int refclk;
5663 5720
5664 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5665 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5666 DPLL_VCO_ENABLE;
5667 if (pipe != PIPE_A)
5668 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5669
5670 crtc->config.dpll_hw_state.dpll_md =
5671 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5672
5673 bestn = crtc->config.dpll.n; 5721 bestn = crtc->config.dpll.n;
5674 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; 5722 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5675 bestm1 = crtc->config.dpll.m1; 5723 bestm1 = crtc->config.dpll.m1;
@@ -6225,7 +6273,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
6225 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; 6273 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6226 6274
6227 val = I915_READ(DSPSTRIDE(pipe)); 6275 val = I915_READ(DSPSTRIDE(pipe));
6228 crtc->base.primary->fb->pitches[0] = val & 0xffffff80; 6276 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6229 6277
6230 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, 6278 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6231 plane_config->tiled); 6279 plane_config->tiled);
@@ -6357,7 +6405,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6357static void ironlake_init_pch_refclk(struct drm_device *dev) 6405static void ironlake_init_pch_refclk(struct drm_device *dev)
6358{ 6406{
6359 struct drm_i915_private *dev_priv = dev->dev_private; 6407 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct drm_mode_config *mode_config = &dev->mode_config;
6361 struct intel_encoder *encoder; 6408 struct intel_encoder *encoder;
6362 u32 val, final; 6409 u32 val, final;
6363 bool has_lvds = false; 6410 bool has_lvds = false;
@@ -6367,8 +6414,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
6367 bool can_ssc = false; 6414 bool can_ssc = false;
6368 6415
6369 /* We need to take the global config into account */ 6416 /* We need to take the global config into account */
6370 list_for_each_entry(encoder, &mode_config->encoder_list, 6417 for_each_intel_encoder(dev, encoder) {
6371 base.head) {
6372 switch (encoder->type) { 6418 switch (encoder->type) {
6373 case INTEL_OUTPUT_LVDS: 6419 case INTEL_OUTPUT_LVDS:
6374 has_panel = true; 6420 has_panel = true;
@@ -6675,11 +6721,10 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
6675 6721
6676static void lpt_init_pch_refclk(struct drm_device *dev) 6722static void lpt_init_pch_refclk(struct drm_device *dev)
6677{ 6723{
6678 struct drm_mode_config *mode_config = &dev->mode_config;
6679 struct intel_encoder *encoder; 6724 struct intel_encoder *encoder;
6680 bool has_vga = false; 6725 bool has_vga = false;
6681 6726
6682 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 6727 for_each_intel_encoder(dev, encoder) {
6683 switch (encoder->type) { 6728 switch (encoder->type) {
6684 case INTEL_OUTPUT_ANALOG: 6729 case INTEL_OUTPUT_ANALOG:
6685 has_vga = true; 6730 has_vga = true;
@@ -7135,7 +7180,8 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7135 7180
7136static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, 7181static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7137 enum transcoder transcoder, 7182 enum transcoder transcoder,
7138 struct intel_link_m_n *m_n) 7183 struct intel_link_m_n *m_n,
7184 struct intel_link_m_n *m2_n2)
7139{ 7185{
7140 struct drm_device *dev = crtc->base.dev; 7186 struct drm_device *dev = crtc->base.dev;
7141 struct drm_i915_private *dev_priv = dev->dev_private; 7187 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7149,6 +7195,20 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7149 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); 7195 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7150 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) 7196 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7151 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; 7197 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7198 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7199 * gen < 8) and if DRRS is supported (to make sure the
7200 * registers are not unnecessarily read).
7201 */
7202 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7203 crtc->config.has_drrs) {
7204 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7205 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7206 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7207 & ~TU_SIZE_MASK;
7208 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7209 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7210 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7211 }
7152 } else { 7212 } else {
7153 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); 7213 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7154 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); 7214 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
@@ -7167,14 +7227,15 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
7167 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); 7227 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7168 else 7228 else
7169 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 7229 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7170 &pipe_config->dp_m_n); 7230 &pipe_config->dp_m_n,
7231 &pipe_config->dp_m2_n2);
7171} 7232}
7172 7233
7173static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, 7234static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7174 struct intel_crtc_config *pipe_config) 7235 struct intel_crtc_config *pipe_config)
7175{ 7236{
7176 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 7237 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7177 &pipe_config->fdi_m_n); 7238 &pipe_config->fdi_m_n, NULL);
7178} 7239}
7179 7240
7180static void ironlake_get_pfit_config(struct intel_crtc *crtc, 7241static void ironlake_get_pfit_config(struct intel_crtc *crtc,
@@ -7245,7 +7306,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
7245 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; 7306 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7246 7307
7247 val = I915_READ(DSPSTRIDE(pipe)); 7308 val = I915_READ(DSPSTRIDE(pipe));
7248 crtc->base.primary->fb->pitches[0] = val & 0xffffff80; 7309 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7249 7310
7250 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, 7311 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7251 plane_config->tiled); 7312 plane_config->tiled);
@@ -7605,6 +7666,22 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7605 return 0; 7666 return 0;
7606} 7667}
7607 7668
7669static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7670 enum port port,
7671 struct intel_crtc_config *pipe_config)
7672{
7673 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7674
7675 switch (pipe_config->ddi_pll_sel) {
7676 case PORT_CLK_SEL_WRPLL1:
7677 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7678 break;
7679 case PORT_CLK_SEL_WRPLL2:
7680 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7681 break;
7682 }
7683}
7684
7608static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 7685static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7609 struct intel_crtc_config *pipe_config) 7686 struct intel_crtc_config *pipe_config)
7610{ 7687{
@@ -7618,16 +7695,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7618 7695
7619 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 7696 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7620 7697
7621 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); 7698 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7622
7623 switch (pipe_config->ddi_pll_sel) {
7624 case PORT_CLK_SEL_WRPLL1:
7625 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7626 break;
7627 case PORT_CLK_SEL_WRPLL2:
7628 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7629 break;
7630 }
7631 7699
7632 if (pipe_config->shared_dpll >= 0) { 7700 if (pipe_config->shared_dpll >= 0) {
7633 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; 7701 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
@@ -9824,8 +9892,7 @@ static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9824 to_intel_encoder(connector->base.encoder); 9892 to_intel_encoder(connector->base.encoder);
9825 } 9893 }
9826 9894
9827 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9895 for_each_intel_encoder(dev, encoder) {
9828 base.head) {
9829 encoder->new_crtc = 9896 encoder->new_crtc =
9830 to_intel_crtc(encoder->base.crtc); 9897 to_intel_crtc(encoder->base.crtc);
9831 } 9898 }
@@ -9856,8 +9923,7 @@ static void intel_modeset_commit_output_state(struct drm_device *dev)
9856 connector->base.encoder = &connector->new_encoder->base; 9923 connector->base.encoder = &connector->new_encoder->base;
9857 } 9924 }
9858 9925
9859 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9926 for_each_intel_encoder(dev, encoder) {
9860 base.head) {
9861 encoder->base.crtc = &encoder->new_crtc->base; 9927 encoder->base.crtc = &encoder->new_crtc->base;
9862 } 9928 }
9863 9929
@@ -9984,6 +10050,15 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
9984 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, 10050 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9985 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, 10051 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9986 pipe_config->dp_m_n.tu); 10052 pipe_config->dp_m_n.tu);
10053
10054 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10055 pipe_config->has_dp_encoder,
10056 pipe_config->dp_m2_n2.gmch_m,
10057 pipe_config->dp_m2_n2.gmch_n,
10058 pipe_config->dp_m2_n2.link_m,
10059 pipe_config->dp_m2_n2.link_n,
10060 pipe_config->dp_m2_n2.tu);
10061
9987 DRM_DEBUG_KMS("requested mode:\n"); 10062 DRM_DEBUG_KMS("requested mode:\n");
9988 drm_mode_debug_printmodeline(&pipe_config->requested_mode); 10063 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9989 DRM_DEBUG_KMS("adjusted mode:\n"); 10064 DRM_DEBUG_KMS("adjusted mode:\n");
@@ -10018,8 +10093,7 @@ static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10018 struct drm_device *dev = crtc->base.dev; 10093 struct drm_device *dev = crtc->base.dev;
10019 struct intel_encoder *source_encoder; 10094 struct intel_encoder *source_encoder;
10020 10095
10021 list_for_each_entry(source_encoder, 10096 for_each_intel_encoder(dev, source_encoder) {
10022 &dev->mode_config.encoder_list, base.head) {
10023 if (source_encoder->new_crtc != crtc) 10097 if (source_encoder->new_crtc != crtc)
10024 continue; 10098 continue;
10025 10099
@@ -10035,8 +10109,7 @@ static bool check_encoder_cloning(struct intel_crtc *crtc)
10035 struct drm_device *dev = crtc->base.dev; 10109 struct drm_device *dev = crtc->base.dev;
10036 struct intel_encoder *encoder; 10110 struct intel_encoder *encoder;
10037 10111
10038 list_for_each_entry(encoder, 10112 for_each_intel_encoder(dev, encoder) {
10039 &dev->mode_config.encoder_list, base.head) {
10040 if (encoder->new_crtc != crtc) 10113 if (encoder->new_crtc != crtc)
10041 continue; 10114 continue;
10042 10115
@@ -10120,8 +10193,7 @@ encoder_retry:
10120 * adjust it according to limitations or connector properties, and also 10193 * adjust it according to limitations or connector properties, and also
10121 * a chance to reject the mode entirely. 10194 * a chance to reject the mode entirely.
10122 */ 10195 */
10123 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10196 for_each_intel_encoder(dev, encoder) {
10124 base.head) {
10125 10197
10126 if (&encoder->new_crtc->base != crtc) 10198 if (&encoder->new_crtc->base != crtc)
10127 continue; 10199 continue;
@@ -10199,8 +10271,7 @@ intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10199 1 << connector->new_encoder->new_crtc->pipe; 10271 1 << connector->new_encoder->new_crtc->pipe;
10200 } 10272 }
10201 10273
10202 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10274 for_each_intel_encoder(dev, encoder) {
10203 base.head) {
10204 if (encoder->base.crtc == &encoder->new_crtc->base) 10275 if (encoder->base.crtc == &encoder->new_crtc->base)
10205 continue; 10276 continue;
10206 10277
@@ -10274,8 +10345,7 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10274 struct intel_crtc *intel_crtc; 10345 struct intel_crtc *intel_crtc;
10275 struct drm_connector *connector; 10346 struct drm_connector *connector;
10276 10347
10277 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, 10348 for_each_intel_encoder(dev, intel_encoder) {
10278 base.head) {
10279 if (!intel_encoder->base.crtc) 10349 if (!intel_encoder->base.crtc)
10280 continue; 10350 continue;
10281 10351
@@ -10364,6 +10434,22 @@ intel_pipe_config_compare(struct drm_device *dev,
10364 return false; \ 10434 return false; \
10365 } 10435 }
10366 10436
10437/* This is required for BDW+ where there is only one set of registers for
10438 * switching between high and low RR.
10439 * This macro can be used whenever a comparison has to be made between one
10440 * hw state and multiple sw state variables.
10441 */
10442#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10443 if ((current_config->name != pipe_config->name) && \
10444 (current_config->alt_name != pipe_config->name)) { \
10445 DRM_ERROR("mismatch in " #name " " \
10446 "(expected %i or %i, found %i)\n", \
10447 current_config->name, \
10448 current_config->alt_name, \
10449 pipe_config->name); \
10450 return false; \
10451 }
10452
10367#define PIPE_CONF_CHECK_FLAGS(name, mask) \ 10453#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10368 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 10454 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10369 DRM_ERROR("mismatch in " #name "(" #mask ") " \ 10455 DRM_ERROR("mismatch in " #name "(" #mask ") " \
@@ -10396,11 +10482,28 @@ intel_pipe_config_compare(struct drm_device *dev,
10396 PIPE_CONF_CHECK_I(fdi_m_n.tu); 10482 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10397 10483
10398 PIPE_CONF_CHECK_I(has_dp_encoder); 10484 PIPE_CONF_CHECK_I(has_dp_encoder);
10399 PIPE_CONF_CHECK_I(dp_m_n.gmch_m); 10485
10400 PIPE_CONF_CHECK_I(dp_m_n.gmch_n); 10486 if (INTEL_INFO(dev)->gen < 8) {
10401 PIPE_CONF_CHECK_I(dp_m_n.link_m); 10487 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10402 PIPE_CONF_CHECK_I(dp_m_n.link_n); 10488 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10403 PIPE_CONF_CHECK_I(dp_m_n.tu); 10489 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10490 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10491 PIPE_CONF_CHECK_I(dp_m_n.tu);
10492
10493 if (current_config->has_drrs) {
10494 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10495 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10496 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10497 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10498 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10499 }
10500 } else {
10501 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10502 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10503 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10504 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10505 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10506 }
10404 10507
10405 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); 10508 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10406 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); 10509 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
@@ -10486,6 +10589,7 @@ intel_pipe_config_compare(struct drm_device *dev,
10486 10589
10487#undef PIPE_CONF_CHECK_X 10590#undef PIPE_CONF_CHECK_X
10488#undef PIPE_CONF_CHECK_I 10591#undef PIPE_CONF_CHECK_I
10592#undef PIPE_CONF_CHECK_I_ALT
10489#undef PIPE_CONF_CHECK_FLAGS 10593#undef PIPE_CONF_CHECK_FLAGS
10490#undef PIPE_CONF_CHECK_CLOCK_FUZZY 10594#undef PIPE_CONF_CHECK_CLOCK_FUZZY
10491#undef PIPE_CONF_QUIRK 10595#undef PIPE_CONF_QUIRK
@@ -10515,8 +10619,7 @@ check_encoder_state(struct drm_device *dev)
10515 struct intel_encoder *encoder; 10619 struct intel_encoder *encoder;
10516 struct intel_connector *connector; 10620 struct intel_connector *connector;
10517 10621
10518 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10622 for_each_intel_encoder(dev, encoder) {
10519 base.head) {
10520 bool enabled = false; 10623 bool enabled = false;
10521 bool active = false; 10624 bool active = false;
10522 enum pipe pipe, tracked_pipe; 10625 enum pipe pipe, tracked_pipe;
@@ -10595,8 +10698,7 @@ check_crtc_state(struct drm_device *dev)
10595 WARN(crtc->active && !crtc->base.enabled, 10698 WARN(crtc->active && !crtc->base.enabled,
10596 "active crtc, but not enabled in sw tracking\n"); 10699 "active crtc, but not enabled in sw tracking\n");
10597 10700
10598 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10701 for_each_intel_encoder(dev, encoder) {
10599 base.head) {
10600 if (encoder->base.crtc != &crtc->base) 10702 if (encoder->base.crtc != &crtc->base)
10601 continue; 10703 continue;
10602 enabled = true; 10704 enabled = true;
@@ -10618,8 +10720,7 @@ check_crtc_state(struct drm_device *dev)
10618 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 10720 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10619 active = crtc->active; 10721 active = crtc->active;
10620 10722
10621 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 10723 for_each_intel_encoder(dev, encoder) {
10622 base.head) {
10623 enum pipe pipe; 10724 enum pipe pipe;
10624 if (encoder->base.crtc != &crtc->base) 10725 if (encoder->base.crtc != &crtc->base)
10625 continue; 10726 continue;
@@ -10987,7 +11088,7 @@ static void intel_set_config_restore_state(struct drm_device *dev,
10987 } 11088 }
10988 11089
10989 count = 0; 11090 count = 0;
10990 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 11091 for_each_intel_encoder(dev, encoder) {
10991 encoder->new_crtc = 11092 encoder->new_crtc =
10992 to_intel_crtc(config->save_encoder_crtcs[count++]); 11093 to_intel_crtc(config->save_encoder_crtcs[count++]);
10993 } 11094 }
@@ -11146,8 +11247,7 @@ intel_modeset_stage_output_state(struct drm_device *dev,
11146 } 11247 }
11147 11248
11148 /* Check for any encoders that needs to be disabled. */ 11249 /* Check for any encoders that needs to be disabled. */
11149 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 11250 for_each_intel_encoder(dev, encoder) {
11150 base.head) {
11151 int num_connectors = 0; 11251 int num_connectors = 0;
11152 list_for_each_entry(connector, 11252 list_for_each_entry(connector,
11153 &dev->mode_config.connector_list, 11253 &dev->mode_config.connector_list,
@@ -11180,9 +11280,7 @@ intel_modeset_stage_output_state(struct drm_device *dev,
11180 for_each_intel_crtc(dev, crtc) { 11280 for_each_intel_crtc(dev, crtc) {
11181 crtc->new_enabled = false; 11281 crtc->new_enabled = false;
11182 11282
11183 list_for_each_entry(encoder, 11283 for_each_intel_encoder(dev, encoder) {
11184 &dev->mode_config.encoder_list,
11185 base.head) {
11186 if (encoder->new_crtc == crtc) { 11284 if (encoder->new_crtc == crtc) {
11187 crtc->new_enabled = true; 11285 crtc->new_enabled = true;
11188 break; 11286 break;
@@ -11219,7 +11317,7 @@ static void disable_crtc_nofb(struct intel_crtc *crtc)
11219 connector->new_encoder = NULL; 11317 connector->new_encoder = NULL;
11220 } 11318 }
11221 11319
11222 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 11320 for_each_intel_encoder(dev, encoder) {
11223 if (encoder->new_crtc == crtc) 11321 if (encoder->new_crtc == crtc)
11224 encoder->new_crtc = NULL; 11322 encoder->new_crtc = NULL;
11225 } 11323 }
@@ -11790,8 +11888,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
11790 intel_crtc->cursor_base = ~0; 11888 intel_crtc->cursor_base = ~0;
11791 intel_crtc->cursor_cntl = ~0; 11889 intel_crtc->cursor_cntl = ~0;
11792 11890
11793 init_waitqueue_head(&intel_crtc->vbl_wait);
11794
11795 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 11891 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11796 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); 11892 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11797 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; 11893 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
@@ -11853,8 +11949,7 @@ static int intel_encoder_clones(struct intel_encoder *encoder)
11853 int index_mask = 0; 11949 int index_mask = 0;
11854 int entry = 0; 11950 int entry = 0;
11855 11951
11856 list_for_each_entry(source_encoder, 11952 for_each_intel_encoder(dev, source_encoder) {
11857 &dev->mode_config.encoder_list, base.head) {
11858 if (encoders_cloneable(encoder, source_encoder)) 11953 if (encoders_cloneable(encoder, source_encoder))
11859 index_mask |= (1 << entry); 11954 index_mask |= (1 << entry);
11860 11955
@@ -12043,7 +12138,7 @@ static void intel_setup_outputs(struct drm_device *dev)
12043 12138
12044 intel_edp_psr_init(dev); 12139 intel_edp_psr_init(dev);
12045 12140
12046 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 12141 for_each_intel_encoder(dev, encoder) {
12047 encoder->base.possible_crtcs = encoder->crtc_mask; 12142 encoder->base.possible_crtcs = encoder->crtc_mask;
12048 encoder->base.possible_clones = 12143 encoder->base.possible_clones =
12049 intel_encoder_clones(encoder); 12144 intel_encoder_clones(encoder);
@@ -12537,8 +12632,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
12537 12632
12538 intel_init_clock_gating(dev); 12633 intel_init_clock_gating(dev);
12539 12634
12540 intel_reset_dpio(dev);
12541
12542 intel_enable_gt_powersave(dev); 12635 intel_enable_gt_powersave(dev);
12543} 12636}
12544 12637
@@ -12609,7 +12702,6 @@ void intel_modeset_init(struct drm_device *dev)
12609 } 12702 }
12610 12703
12611 intel_init_dpio(dev); 12704 intel_init_dpio(dev);
12612 intel_reset_dpio(dev);
12613 12705
12614 intel_shared_dpll_init(dev); 12706 intel_shared_dpll_init(dev);
12615 12707
@@ -12938,8 +13030,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
12938 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 13030 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12939 } 13031 }
12940 13032
12941 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 13033 for_each_intel_encoder(dev, encoder) {
12942 base.head) {
12943 pipe = 0; 13034 pipe = 0;
12944 13035
12945 if (encoder->get_hw_state(encoder, &pipe)) { 13036 if (encoder->get_hw_state(encoder, &pipe)) {
@@ -13003,8 +13094,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
13003 } 13094 }
13004 13095
13005 /* HW state is read out, now we need to sanitize this mess. */ 13096 /* HW state is read out, now we need to sanitize this mess. */
13006 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 13097 for_each_intel_encoder(dev, encoder) {
13007 base.head) {
13008 intel_sanitize_encoder(encoder); 13098 intel_sanitize_encoder(encoder);
13009 } 13099 }
13010 13100
@@ -13371,3 +13461,25 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13371 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); 13461 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13372 } 13462 }
13373} 13463}
13464
13465void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13466{
13467 struct intel_crtc *crtc;
13468
13469 for_each_intel_crtc(dev, crtc) {
13470 struct intel_unpin_work *work;
13471 unsigned long irqflags;
13472
13473 spin_lock_irqsave(&dev->event_lock, irqflags);
13474
13475 work = crtc->unpin_work;
13476
13477 if (work && work->event &&
13478 work->event->base.file_priv == file) {
13479 kfree(work->event);
13480 work->event = NULL;
13481 }
13482
13483 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13484 }
13485}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 67cfed6d911a..6db84bf0a92a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -828,20 +828,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
828 } 828 }
829} 829}
830 830
831static void
832intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
833{
834 struct drm_device *dev = crtc->base.dev;
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 enum transcoder transcoder = crtc->config.cpu_transcoder;
837
838 I915_WRITE(PIPE_DATA_M2(transcoder),
839 TU_SIZE(m_n->tu) | m_n->gmch_m);
840 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
841 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
842 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
843}
844
845bool 831bool
846intel_dp_compute_config(struct intel_encoder *encoder, 832intel_dp_compute_config(struct intel_encoder *encoder,
847 struct intel_crtc_config *pipe_config) 833 struct intel_crtc_config *pipe_config)
@@ -867,6 +853,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
867 pipe_config->has_pch_encoder = true; 853 pipe_config->has_pch_encoder = true;
868 854
869 pipe_config->has_dp_encoder = true; 855 pipe_config->has_dp_encoder = true;
856 pipe_config->has_drrs = false;
870 pipe_config->has_audio = intel_dp->has_audio; 857 pipe_config->has_audio = intel_dp->has_audio;
871 858
872 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 859 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
@@ -970,13 +957,14 @@ found:
970 957
971 if (intel_connector->panel.downclock_mode != NULL && 958 if (intel_connector->panel.downclock_mode != NULL &&
972 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { 959 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
960 pipe_config->has_drrs = true;
973 intel_link_compute_m_n(bpp, lane_count, 961 intel_link_compute_m_n(bpp, lane_count,
974 intel_connector->panel.downclock_mode->clock, 962 intel_connector->panel.downclock_mode->clock,
975 pipe_config->port_clock, 963 pipe_config->port_clock,
976 &pipe_config->dp_m2_n2); 964 &pipe_config->dp_m2_n2);
977 } 965 }
978 966
979 if (HAS_DDI(dev)) 967 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
980 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); 968 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
981 else 969 else
982 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 970 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
@@ -2293,6 +2281,8 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2293 enum pipe pipe = intel_crtc->pipe; 2281 enum pipe pipe = intel_crtc->pipe;
2294 u32 val; 2282 u32 val;
2295 2283
2284 intel_dp_prepare(encoder);
2285
2296 mutex_lock(&dev_priv->dpio_lock); 2286 mutex_lock(&dev_priv->dpio_lock);
2297 2287
2298 /* program left/right clock distribution */ 2288 /* program left/right clock distribution */
@@ -2659,8 +2649,8 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2659 /* Program swing margin */ 2649 /* Program swing margin */
2660 for (i = 0; i < 4; i++) { 2650 for (i = 0; i < 4; i++) {
2661 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2651 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2662 val &= ~DPIO_SWING_MARGIN_MASK; 2652 val &= ~DPIO_SWING_MARGIN000_MASK;
2663 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; 2653 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2664 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2654 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2665 } 2655 }
2666 2656
@@ -2971,7 +2961,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
2971 } 2961 }
2972 2962
2973 } else { 2963 } else {
2974 *DP &= ~DP_LINK_TRAIN_MASK; 2964 if (IS_CHERRYVIEW(dev))
2965 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2966 else
2967 *DP &= ~DP_LINK_TRAIN_MASK;
2975 2968
2976 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2969 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2977 case DP_TRAINING_PATTERN_DISABLE: 2970 case DP_TRAINING_PATTERN_DISABLE:
@@ -2984,8 +2977,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
2984 *DP |= DP_LINK_TRAIN_PAT_2; 2977 *DP |= DP_LINK_TRAIN_PAT_2;
2985 break; 2978 break;
2986 case DP_TRAINING_PATTERN_3: 2979 case DP_TRAINING_PATTERN_3:
2987 DRM_ERROR("DP training pattern 3 not supported\n"); 2980 if (IS_CHERRYVIEW(dev)) {
2988 *DP |= DP_LINK_TRAIN_PAT_2; 2981 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2982 } else {
2983 DRM_ERROR("DP training pattern 3 not supported\n");
2984 *DP |= DP_LINK_TRAIN_PAT_2;
2985 }
2989 break; 2986 break;
2990 } 2987 }
2991 } 2988 }
@@ -3272,7 +3269,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
3272 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3269 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3273 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 3270 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3274 } else { 3271 } else {
3275 DP &= ~DP_LINK_TRAIN_MASK; 3272 if (IS_CHERRYVIEW(dev))
3273 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3274 else
3275 DP &= ~DP_LINK_TRAIN_MASK;
3276 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 3276 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3277 } 3277 }
3278 POSTING_READ(intel_dp->output_reg); 3278 POSTING_READ(intel_dp->output_reg);
@@ -4415,7 +4415,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4415 val = I915_READ(reg); 4415 val = I915_READ(reg);
4416 if (index > DRRS_HIGH_RR) { 4416 if (index > DRRS_HIGH_RR) {
4417 val |= PIPECONF_EDP_RR_MODE_SWITCH; 4417 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4418 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); 4418 intel_dp_set_m_n(intel_crtc);
4419 } else { 4419 } else {
4420 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 4420 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4421 } 4421 }
@@ -4455,7 +4455,7 @@ intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4455 } 4455 }
4456 4456
4457 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 4457 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4458 DRM_INFO("VBT doesn't support DRRS\n"); 4458 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4459 return NULL; 4459 return NULL;
4460 } 4460 }
4461 4461
@@ -4463,7 +4463,7 @@ intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4463 (dev, fixed_mode, connector); 4463 (dev, fixed_mode, connector);
4464 4464
4465 if (!downclock_mode) { 4465 if (!downclock_mode) {
4466 DRM_INFO("DRRS not supported\n"); 4466 DRM_DEBUG_KMS("DRRS not supported\n");
4467 return NULL; 4467 return NULL;
4468 } 4468 }
4469 4469
@@ -4474,7 +4474,7 @@ intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4474 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; 4474 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4475 4475
4476 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; 4476 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4477 DRM_INFO("seamless DRRS supported for eDP panel.\n"); 4477 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4478 return downclock_mode; 4478 return downclock_mode;
4479} 4479}
4480 4480
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b8c8bbd8e5f9..70cddaf29ae3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -330,6 +330,7 @@ struct intel_crtc_config {
330 330
331 /* m2_n2 for eDP downclock */ 331 /* m2_n2 for eDP downclock */
332 struct intel_link_m_n dp_m2_n2; 332 struct intel_link_m_n dp_m2_n2;
333 bool has_drrs;
333 334
334 /* 335 /*
335 * Frequence the dpll for the port should run at. Differs from the 336 * Frequence the dpll for the port should run at. Differs from the
@@ -430,8 +431,6 @@ struct intel_crtc {
430 struct intel_pipe_wm active; 431 struct intel_pipe_wm active;
431 } wm; 432 } wm;
432 433
433 wait_queue_head_t vbl_wait;
434
435 int scanline_offset; 434 int scanline_offset;
436 struct intel_mmio_flip mmio_flip; 435 struct intel_mmio_flip mmio_flip;
437}; 436};
@@ -455,6 +454,7 @@ struct intel_plane {
455 unsigned int crtc_w, crtc_h; 454 unsigned int crtc_w, crtc_h;
456 uint32_t src_x, src_y; 455 uint32_t src_x, src_y;
457 uint32_t src_w, src_h; 456 uint32_t src_w, src_h;
457 unsigned int rotation;
458 458
459 /* Since we need to change the watermarks before/after 459 /* Since we need to change the watermarks before/after
460 * enabling/disabling the planes, we need to store the parameters here 460 * enabling/disabling the planes, we need to store the parameters here
@@ -882,6 +882,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
882void hsw_disable_pc8(struct drm_i915_private *dev_priv); 882void hsw_disable_pc8(struct drm_i915_private *dev_priv);
883void intel_dp_get_m_n(struct intel_crtc *crtc, 883void intel_dp_get_m_n(struct intel_crtc *crtc,
884 struct intel_crtc_config *pipe_config); 884 struct intel_crtc_config *pipe_config);
885void intel_dp_set_m_n(struct intel_crtc *crtc);
885int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 886int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
886void 887void
887ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, 888ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
@@ -896,7 +897,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
896 struct intel_crtc_config *pipe_config); 897 struct intel_crtc_config *pipe_config);
897int intel_format_to_fourcc(int format); 898int intel_format_to_fourcc(int format);
898void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); 899void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
899 900void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
900 901
901/* intel_dp.c */ 902/* intel_dp.c */
902void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); 903void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
@@ -1091,7 +1092,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1091int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); 1092int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1092void intel_flush_primary_plane(struct drm_i915_private *dev_priv, 1093void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1093 enum plane plane); 1094 enum plane plane);
1094void intel_plane_restore(struct drm_plane *plane); 1095int intel_plane_restore(struct drm_plane *plane);
1095void intel_plane_disable(struct drm_plane *plane); 1096void intel_plane_disable(struct drm_plane *plane);
1096int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 1097int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1097 struct drm_file *file_priv); 1098 struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 670c29a7b5dd..5bd9e09ad3c5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -184,7 +184,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
184 184
185 /* update the hw state for DPLL */ 185 /* update the hw state for DPLL */
186 intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | 186 intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
187 DPLL_REFA_CLK_ENABLE_VLV; 187 DPLL_REFA_CLK_ENABLE_VLV;
188 188
189 tmp = I915_READ(DSPCLK_GATE_D); 189 tmp = I915_READ(DSPCLK_GATE_D);
190 tmp |= DPOUNIT_CLOCK_GATE_DISABLE; 190 tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
@@ -259,8 +259,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
259 temp = I915_READ(MIPI_CTRL(pipe)); 259 temp = I915_READ(MIPI_CTRL(pipe));
260 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 260 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
261 I915_WRITE(MIPI_CTRL(pipe), temp | 261 I915_WRITE(MIPI_CTRL(pipe), temp |
262 intel_dsi->escape_clk_div << 262 intel_dsi->escape_clk_div <<
263 ESCAPE_CLOCK_DIVIDER_SHIFT); 263 ESCAPE_CLOCK_DIVIDER_SHIFT);
264 264
265 I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); 265 I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
266 266
@@ -297,7 +297,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
297 usleep_range(2000, 2500); 297 usleep_range(2000, 2500);
298 298
299 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) 299 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
300 == 0x00000), 30)) 300 == 0x00000), 30))
301 DRM_ERROR("DSI LP not going Low\n"); 301 DRM_ERROR("DSI LP not going Low\n");
302 302
303 val = I915_READ(MIPI_PORT_CTRL(pipe)); 303 val = I915_READ(MIPI_PORT_CTRL(pipe));
@@ -423,9 +423,11 @@ static u16 txclkesc(u32 divider, unsigned int us)
423} 423}
424 424
425/* return pixels in terms of txbyteclkhs */ 425/* return pixels in terms of txbyteclkhs */
426static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) 426static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
427 u16 burst_mode_ratio)
427{ 428{
428 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); 429 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
430 8 * 100), lane_count);
429} 431}
430 432
431static void set_dsi_timings(struct drm_encoder *encoder, 433static void set_dsi_timings(struct drm_encoder *encoder,
@@ -451,10 +453,12 @@ static void set_dsi_timings(struct drm_encoder *encoder,
451 vbp = mode->vtotal - mode->vsync_end; 453 vbp = mode->vtotal - mode->vsync_end;
452 454
453 /* horizontal values are in terms of high speed byte clock */ 455 /* horizontal values are in terms of high speed byte clock */
454 hactive = txbyteclkhs(hactive, bpp, lane_count); 456 hactive = txbyteclkhs(hactive, bpp, lane_count,
455 hfp = txbyteclkhs(hfp, bpp, lane_count); 457 intel_dsi->burst_mode_ratio);
456 hsync = txbyteclkhs(hsync, bpp, lane_count); 458 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
457 hbp = txbyteclkhs(hbp, bpp, lane_count); 459 hsync = txbyteclkhs(hsync, bpp, lane_count,
460 intel_dsi->burst_mode_ratio);
461 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
458 462
459 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); 463 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
460 I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); 464 I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
@@ -541,12 +545,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
541 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 545 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
542 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), 546 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
543 txbyteclkhs(adjusted_mode->htotal, bpp, 547 txbyteclkhs(adjusted_mode->htotal, bpp,
544 intel_dsi->lane_count) + 1); 548 intel_dsi->lane_count,
549 intel_dsi->burst_mode_ratio) + 1);
545 } else { 550 } else {
546 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), 551 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
547 txbyteclkhs(adjusted_mode->vtotal * 552 txbyteclkhs(adjusted_mode->vtotal *
548 adjusted_mode->htotal, 553 adjusted_mode->htotal,
549 bpp, intel_dsi->lane_count) + 1); 554 bpp, intel_dsi->lane_count,
555 intel_dsi->burst_mode_ratio) + 1);
550 } 556 }
551 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); 557 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
552 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); 558 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
@@ -576,7 +582,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
576 * XXX: write MIPI_STOP_STATE_STALL? 582 * XXX: write MIPI_STOP_STATE_STALL?
577 */ 583 */
578 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 584 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
579 intel_dsi->hs_to_lp_count); 585 intel_dsi->hs_to_lp_count);
580 586
581 /* XXX: low power clock equivalence in terms of byte clock. the number 587 /* XXX: low power clock equivalence in terms of byte clock. the number
582 * of byte clocks occupied in one low power clock. based on txbyteclkhs 588 * of byte clocks occupied in one low power clock. based on txbyteclkhs
@@ -601,10 +607,10 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
601 * 64 like 1366 x 768. Enable RANDOM resolution support for such 607 * 64 like 1366 x 768. Enable RANDOM resolution support for such
602 * panels by default */ 608 * panels by default */
603 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), 609 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
604 intel_dsi->video_frmt_cfg_bits | 610 intel_dsi->video_frmt_cfg_bits |
605 intel_dsi->video_mode_format | 611 intel_dsi->video_mode_format |
606 IP_TG_CONFIG | 612 IP_TG_CONFIG |
607 RANDOM_DPI_DISPLAY_RESOLUTION); 613 RANDOM_DPI_DISPLAY_RESOLUTION);
608} 614}
609 615
610static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) 616static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index fd51867fd0d3..657eb5c1b9d8 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -116,6 +116,8 @@ struct intel_dsi {
116 u16 clk_hs_to_lp_count; 116 u16 clk_hs_to_lp_count;
117 117
118 u16 init_count; 118 u16 init_count;
119 u32 pclk;
120 u16 burst_mode_ratio;
119 121
120 /* all delays in ms */ 122 /* all delays in ms */
121 u16 backlight_off_delay; 123 u16 backlight_off_delay;
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 7f1430ac8543..f4767fd2ebeb 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -430,7 +430,7 @@ void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
430 u32 mask; 430 u32 mask;
431 431
432 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 432 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
433 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 433 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
434 434
435 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100)) 435 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 100))
436 DRM_ERROR("DPI FIFOs are not empty\n"); 436 DRM_ERROR("DPI FIFOs are not empty\n");
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 47c7584a4aa0..f6bdd44069ce 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -271,6 +271,8 @@ static bool generic_init(struct intel_dsi_device *dsi)
271 u32 ths_prepare_ns, tclk_trail_ns; 271 u32 ths_prepare_ns, tclk_trail_ns;
272 u32 tclk_prepare_clkzero, ths_prepare_hszero; 272 u32 tclk_prepare_clkzero, ths_prepare_hszero;
273 u32 lp_to_hs_switch, hs_to_lp_switch; 273 u32 lp_to_hs_switch, hs_to_lp_switch;
274 u32 pclk, computed_ddr;
275 u16 burst_mode_ratio;
274 276
275 DRM_DEBUG_KMS("\n"); 277 DRM_DEBUG_KMS("\n");
276 278
@@ -284,8 +286,6 @@ static bool generic_init(struct intel_dsi_device *dsi)
284 else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565) 286 else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
285 bits_per_pixel = 16; 287 bits_per_pixel = 16;
286 288
287 bitrate = (mode->clock * bits_per_pixel) / intel_dsi->lane_count;
288
289 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 289 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
290 intel_dsi->video_mode_format = mipi_config->video_transfer_mode; 290 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
291 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 291 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
@@ -297,6 +297,40 @@ static bool generic_init(struct intel_dsi_device *dsi)
297 intel_dsi->video_frmt_cfg_bits = 297 intel_dsi->video_frmt_cfg_bits =
298 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 298 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
299 299
300 pclk = mode->clock;
301
302 /* Burst Mode Ratio
303 * Target ddr frequency from VBT / non burst ddr freq
304 * multiply by 100 to preserve remainder
305 */
306 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
307 if (mipi_config->target_burst_mode_freq) {
308 computed_ddr =
309 (pclk * bits_per_pixel) / intel_dsi->lane_count;
310
311 if (mipi_config->target_burst_mode_freq <
312 computed_ddr) {
313 DRM_ERROR("Burst mode freq is less than computed\n");
314 return false;
315 }
316
317 burst_mode_ratio = DIV_ROUND_UP(
318 mipi_config->target_burst_mode_freq * 100,
319 computed_ddr);
320
321 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
322 } else {
323 DRM_ERROR("Burst mode target is not set\n");
324 return false;
325 }
326 } else
327 burst_mode_ratio = 100;
328
329 intel_dsi->burst_mode_ratio = burst_mode_ratio;
330 intel_dsi->pclk = pclk;
331
332 bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
333
300 switch (intel_dsi->escape_clk_div) { 334 switch (intel_dsi->escape_clk_div) {
301 case 0: 335 case 0:
302 tlpx_ns = 50; 336 tlpx_ns = 50;
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index d8bb1ea2f0da..fa7a6ca34cd6 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -134,8 +134,7 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode,
134#else 134#else
135 135
136/* Get DSI clock from pixel clock */ 136/* Get DSI clock from pixel clock */
137static u32 dsi_clk_from_pclk(const struct drm_display_mode *mode, 137static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
138 int pixel_format, int lane_count)
139{ 138{
140 u32 dsi_clk_khz; 139 u32 dsi_clk_khz;
141 u32 bpp; 140 u32 bpp;
@@ -156,7 +155,7 @@ static u32 dsi_clk_from_pclk(const struct drm_display_mode *mode,
156 155
157 /* DSI data rate = pixel clock * bits per pixel / lane count 156 /* DSI data rate = pixel clock * bits per pixel / lane count
158 pixel clock is converted from KHz to Hz */ 157 pixel clock is converted from KHz to Hz */
159 dsi_clk_khz = DIV_ROUND_CLOSEST(mode->clock * bpp, lane_count); 158 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
160 159
161 return dsi_clk_khz; 160 return dsi_clk_khz;
162} 161}
@@ -191,7 +190,7 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
191 for (m = 62; m <= 92; m++) { 190 for (m = 62; m <= 92; m++) {
192 for (p = 2; p <= 6; p++) { 191 for (p = 2; p <= 6; p++) {
193 /* Find the optimal m and p divisors 192 /* Find the optimal m and p divisors
194 with minimal error +/- the required clock */ 193 with minimal error +/- the required clock */
195 calc_dsi_clk = (m * ref_clk) / p; 194 calc_dsi_clk = (m * ref_clk) / p;
196 if (calc_dsi_clk == target_dsi_clk) { 195 if (calc_dsi_clk == target_dsi_clk) {
197 calc_m = m; 196 calc_m = m;
@@ -228,15 +227,13 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
228static void vlv_configure_dsi_pll(struct intel_encoder *encoder) 227static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
229{ 228{
230 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 229 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
231 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
232 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
233 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 230 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
234 int ret; 231 int ret;
235 struct dsi_mnp dsi_mnp; 232 struct dsi_mnp dsi_mnp;
236 u32 dsi_clk; 233 u32 dsi_clk;
237 234
238 dsi_clk = dsi_clk_from_pclk(mode, intel_dsi->pixel_format, 235 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
239 intel_dsi->lane_count); 236 intel_dsi->lane_count);
240 237
241 ret = dsi_calc_mnp(dsi_clk, &dsi_mnp); 238 ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
242 if (ret) { 239 if (ret) {
@@ -318,8 +315,8 @@ static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
318 } 315 }
319 316
320 WARN(bpp != pipe_bpp, 317 WARN(bpp != pipe_bpp,
321 "bpp match assertion failure (expected %d, current %d)\n", 318 "bpp match assertion failure (expected %d, current %d)\n",
322 bpp, pipe_bpp); 319 bpp, pipe_bpp);
323} 320}
324 321
325u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) 322u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f9151f6641d9..9169786dbbc3 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -885,7 +885,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
885 if (HAS_GMCH_DISPLAY(dev)) 885 if (HAS_GMCH_DISPLAY(dev))
886 return false; 886 return false;
887 887
888 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 888 for_each_intel_encoder(dev, encoder) {
889 if (encoder->new_crtc != crtc) 889 if (encoder->new_crtc != crtc)
890 continue; 890 continue;
891 891
@@ -1260,6 +1260,8 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1260 enum pipe pipe = intel_crtc->pipe; 1260 enum pipe pipe = intel_crtc->pipe;
1261 u32 val; 1261 u32 val;
1262 1262
1263 intel_hdmi_prepare(encoder);
1264
1263 mutex_lock(&dev_priv->dpio_lock); 1265 mutex_lock(&dev_priv->dpio_lock);
1264 1266
1265 /* program left/right clock distribution */ 1267 /* program left/right clock distribution */
@@ -1429,8 +1431,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1429 1431
1430 for (i = 0; i < 4; i++) { 1432 for (i = 0; i < 4; i++) {
1431 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 1433 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1432 val &= ~DPIO_SWING_MARGIN_MASK; 1434 val &= ~DPIO_SWING_MARGIN000_MASK;
1433 val |= 102 << DPIO_SWING_MARGIN_SHIFT; 1435 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1434 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 1436 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1435 } 1437 }
1436 1438
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 881361c0f27e..1987491723a5 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -823,8 +823,7 @@ bool intel_is_dual_link_lvds(struct drm_device *dev)
823 struct intel_encoder *encoder; 823 struct intel_encoder *encoder;
824 struct intel_lvds_encoder *lvds_encoder; 824 struct intel_lvds_encoder *lvds_encoder;
825 825
826 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 826 for_each_intel_encoder(dev, encoder) {
827 base.head) {
828 if (encoder->type == INTEL_OUTPUT_LVDS) { 827 if (encoder->type == INTEL_OUTPUT_LVDS) {
829 lvds_encoder = to_lvds_encoder(&encoder->base); 828 lvds_encoder = to_lvds_encoder(&encoder->base);
830 829
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 40c12295c0bd..020e9ab567ed 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -309,6 +309,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
309 309
310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; 310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311 311
312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
312 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
313 316
314 if (IS_IVYBRIDGE(dev)) { 317 if (IS_IVYBRIDGE(dev)) {
@@ -1268,33 +1271,27 @@ static bool g4x_compute_srwm(struct drm_device *dev,
1268 display, cursor); 1271 display, cursor);
1269} 1272}
1270 1273
1271static bool vlv_compute_drain_latency(struct drm_device *dev, 1274static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1272 int plane, 1275 int pixel_size,
1273 int *plane_prec_mult, 1276 int *prec_mult,
1274 int *plane_dl, 1277 int *drain_latency)
1275 int *cursor_prec_mult,
1276 int *cursor_dl)
1277{ 1278{
1278 struct drm_crtc *crtc;
1279 int clock, pixel_size;
1280 int entries; 1279 int entries;
1280 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1281 1281
1282 crtc = intel_get_crtc_for_plane(dev, plane); 1282 if (WARN(clock == 0, "Pixel clock is zero!\n"))
1283 if (!intel_crtc_active(crtc))
1284 return false; 1283 return false;
1285 1284
1286 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; 1285 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1287 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ 1286 return false;
1288 1287
1289 entries = (clock / 1000) * pixel_size; 1288 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
1290 *plane_prec_mult = (entries > 128) ? 1289 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1291 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; 1290 DRAIN_LATENCY_PRECISION_32;
1292 *plane_dl = (64 * (*plane_prec_mult) * 4) / entries; 1291 *drain_latency = (64 * (*prec_mult) * 4) / entries;
1293 1292
1294 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ 1293 if (*drain_latency > DRAIN_LATENCY_MASK)
1295 *cursor_prec_mult = (entries > 128) ? 1294 *drain_latency = DRAIN_LATENCY_MASK;
1296 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
1297 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;
1298 1295
1299 return true; 1296 return true;
1300} 1297}
@@ -1307,39 +1304,48 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
1307 * latency value. 1304 * latency value.
1308 */ 1305 */
1309 1306
1310static void vlv_update_drain_latency(struct drm_device *dev) 1307static void vlv_update_drain_latency(struct drm_crtc *crtc)
1311{ 1308{
1312 struct drm_i915_private *dev_priv = dev->dev_private; 1309 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1313 int planea_prec, planea_dl, planeb_prec, planeb_dl; 1310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1314 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; 1311 int pixel_size;
1315 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is 1312 int drain_latency;
1316 either 16 or 32 */ 1313 enum pipe pipe = intel_crtc->pipe;
1314 int plane_prec, prec_mult, plane_dl;
1317 1315
1318 /* For plane A, Cursor A */ 1316 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1319 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, 1317 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1320 &cursor_prec_mult, &cursora_dl)) { 1318 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1321 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1319
1322 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64; 1320 if (!intel_crtc_active(crtc)) {
1323 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1321 I915_WRITE(VLV_DDL(pipe), plane_dl);
1324 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64; 1322 return;
1323 }
1325 1324
1326 I915_WRITE(VLV_DDL1, cursora_prec | 1325 /* Primary plane Drain Latency */
1327 (cursora_dl << DDL_CURSORA_SHIFT) | 1326 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1328 planea_prec | planea_dl); 1327 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1328 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1329 DDL_PLANE_PRECISION_64 :
1330 DDL_PLANE_PRECISION_32;
1331 plane_dl |= plane_prec | drain_latency;
1329 } 1332 }
1330 1333
1331 /* For plane B, Cursor B */ 1334 /* Cursor Drain Latency
1332 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, 1335 * BPP is always 4 for cursor
1333 &cursor_prec_mult, &cursorb_dl)) { 1336 */
1334 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1337 pixel_size = 4;
1335 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
1336 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1337 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
1338 1338
1339 I915_WRITE(VLV_DDL2, cursorb_prec | 1339 /* Program cursor DL only if it is enabled */
1340 (cursorb_dl << DDL_CURSORB_SHIFT) | 1340 if (intel_crtc->cursor_base &&
1341 planeb_prec | planeb_dl); 1341 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1342 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1343 DDL_CURSOR_PRECISION_64 :
1344 DDL_CURSOR_PRECISION_32;
1345 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
1342 } 1346 }
1347
1348 I915_WRITE(VLV_DDL(pipe), plane_dl);
1343} 1349}
1344 1350
1345#define single_plane_enabled(mask) is_power_of_2(mask) 1351#define single_plane_enabled(mask) is_power_of_2(mask)
@@ -1355,7 +1361,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
1355 unsigned int enabled = 0; 1361 unsigned int enabled = 0;
1356 bool cxsr_enabled; 1362 bool cxsr_enabled;
1357 1363
1358 vlv_update_drain_latency(dev); 1364 vlv_update_drain_latency(crtc);
1359 1365
1360 if (g4x_compute_wm0(dev, PIPE_A, 1366 if (g4x_compute_wm0(dev, PIPE_A,
1361 &valleyview_wm_info, latency_ns, 1367 &valleyview_wm_info, latency_ns,
@@ -1387,7 +1393,8 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
1387 plane_sr = cursor_sr = 0; 1393 plane_sr = cursor_sr = 0;
1388 } 1394 }
1389 1395
1390 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1396 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1397 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1391 planea_wm, cursora_wm, 1398 planea_wm, cursora_wm,
1392 planeb_wm, cursorb_wm, 1399 planeb_wm, cursorb_wm,
1393 plane_sr, cursor_sr); 1400 plane_sr, cursor_sr);
@@ -1396,7 +1403,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
1396 (plane_sr << DSPFW_SR_SHIFT) | 1403 (plane_sr << DSPFW_SR_SHIFT) |
1397 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1404 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1398 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1405 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1399 planea_wm); 1406 (planea_wm << DSPFW_PLANEA_SHIFT));
1400 I915_WRITE(DSPFW2, 1407 I915_WRITE(DSPFW2,
1401 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1408 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1402 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1409 (cursora_wm << DSPFW_CURSORA_SHIFT));
@@ -1408,6 +1415,116 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
1408 intel_set_memory_cxsr(dev_priv, true); 1415 intel_set_memory_cxsr(dev_priv, true);
1409} 1416}
1410 1417
1418static void cherryview_update_wm(struct drm_crtc *crtc)
1419{
1420 struct drm_device *dev = crtc->dev;
1421 static const int sr_latency_ns = 12000;
1422 struct drm_i915_private *dev_priv = dev->dev_private;
1423 int planea_wm, planeb_wm, planec_wm;
1424 int cursora_wm, cursorb_wm, cursorc_wm;
1425 int plane_sr, cursor_sr;
1426 int ignore_plane_sr, ignore_cursor_sr;
1427 unsigned int enabled = 0;
1428 bool cxsr_enabled;
1429
1430 vlv_update_drain_latency(crtc);
1431
1432 if (g4x_compute_wm0(dev, PIPE_A,
1433 &valleyview_wm_info, latency_ns,
1434 &valleyview_cursor_wm_info, latency_ns,
1435 &planea_wm, &cursora_wm))
1436 enabled |= 1 << PIPE_A;
1437
1438 if (g4x_compute_wm0(dev, PIPE_B,
1439 &valleyview_wm_info, latency_ns,
1440 &valleyview_cursor_wm_info, latency_ns,
1441 &planeb_wm, &cursorb_wm))
1442 enabled |= 1 << PIPE_B;
1443
1444 if (g4x_compute_wm0(dev, PIPE_C,
1445 &valleyview_wm_info, latency_ns,
1446 &valleyview_cursor_wm_info, latency_ns,
1447 &planec_wm, &cursorc_wm))
1448 enabled |= 1 << PIPE_C;
1449
1450 if (single_plane_enabled(enabled) &&
1451 g4x_compute_srwm(dev, ffs(enabled) - 1,
1452 sr_latency_ns,
1453 &valleyview_wm_info,
1454 &valleyview_cursor_wm_info,
1455 &plane_sr, &ignore_cursor_sr) &&
1456 g4x_compute_srwm(dev, ffs(enabled) - 1,
1457 2*sr_latency_ns,
1458 &valleyview_wm_info,
1459 &valleyview_cursor_wm_info,
1460 &ignore_plane_sr, &cursor_sr)) {
1461 cxsr_enabled = true;
1462 } else {
1463 cxsr_enabled = false;
1464 intel_set_memory_cxsr(dev_priv, false);
1465 plane_sr = cursor_sr = 0;
1466 }
1467
1468 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1469 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1470 "SR: plane=%d, cursor=%d\n",
1471 planea_wm, cursora_wm,
1472 planeb_wm, cursorb_wm,
1473 planec_wm, cursorc_wm,
1474 plane_sr, cursor_sr);
1475
1476 I915_WRITE(DSPFW1,
1477 (plane_sr << DSPFW_SR_SHIFT) |
1478 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1479 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1480 (planea_wm << DSPFW_PLANEA_SHIFT));
1481 I915_WRITE(DSPFW2,
1482 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1483 (cursora_wm << DSPFW_CURSORA_SHIFT));
1484 I915_WRITE(DSPFW3,
1485 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1486 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1487 I915_WRITE(DSPFW9_CHV,
1488 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1489 DSPFW_CURSORC_MASK)) |
1490 (planec_wm << DSPFW_PLANEC_SHIFT) |
1491 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1492
1493 if (cxsr_enabled)
1494 intel_set_memory_cxsr(dev_priv, true);
1495}
1496
1497static void valleyview_update_sprite_wm(struct drm_plane *plane,
1498 struct drm_crtc *crtc,
1499 uint32_t sprite_width,
1500 uint32_t sprite_height,
1501 int pixel_size,
1502 bool enabled, bool scaled)
1503{
1504 struct drm_device *dev = crtc->dev;
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 int pipe = to_intel_plane(plane)->pipe;
1507 int sprite = to_intel_plane(plane)->plane;
1508 int drain_latency;
1509 int plane_prec;
1510 int sprite_dl;
1511 int prec_mult;
1512
1513 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1514 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1515
1516 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1517 &drain_latency)) {
1518 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1519 DDL_SPRITE_PRECISION_64(sprite) :
1520 DDL_SPRITE_PRECISION_32(sprite);
1521 sprite_dl |= plane_prec |
1522 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1523 }
1524
1525 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1526}
1527
1411static void g4x_update_wm(struct drm_crtc *crtc) 1528static void g4x_update_wm(struct drm_crtc *crtc)
1412{ 1529{
1413 struct drm_device *dev = crtc->dev; 1530 struct drm_device *dev = crtc->dev;
@@ -1443,7 +1560,8 @@ static void g4x_update_wm(struct drm_crtc *crtc)
1443 plane_sr = cursor_sr = 0; 1560 plane_sr = cursor_sr = 0;
1444 } 1561 }
1445 1562
1446 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1563 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1564 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1447 planea_wm, cursora_wm, 1565 planea_wm, cursora_wm,
1448 planeb_wm, cursorb_wm, 1566 planeb_wm, cursorb_wm,
1449 plane_sr, cursor_sr); 1567 plane_sr, cursor_sr);
@@ -1452,7 +1570,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
1452 (plane_sr << DSPFW_SR_SHIFT) | 1570 (plane_sr << DSPFW_SR_SHIFT) |
1453 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1571 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1454 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1572 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1455 planea_wm); 1573 (planea_wm << DSPFW_PLANEA_SHIFT));
1456 I915_WRITE(DSPFW2, 1574 I915_WRITE(DSPFW2,
1457 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1575 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1458 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1576 (cursora_wm << DSPFW_CURSORA_SHIFT));
@@ -1526,8 +1644,11 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
1526 1644
1527 /* 965 has limitations... */ 1645 /* 965 has limitations... */
1528 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | 1646 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1529 (8 << 16) | (8 << 8) | (8 << 0)); 1647 (8 << DSPFW_CURSORB_SHIFT) |
1530 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 1648 (8 << DSPFW_PLANEB_SHIFT) |
1649 (8 << DSPFW_PLANEA_SHIFT));
1650 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1651 (8 << DSPFW_PLANEC_SHIFT_OLD));
1531 /* update cursor SR watermark */ 1652 /* update cursor SR watermark */
1532 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1653 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1533 1654
@@ -6252,6 +6373,153 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6252 vlv_set_power_well(dev_priv, power_well, false); 6373 vlv_set_power_well(dev_priv, power_well, false);
6253} 6374}
6254 6375
6376static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6377 struct i915_power_well *power_well)
6378{
6379 enum dpio_phy phy;
6380
6381 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6382 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6383
6384 /*
6385 * Enable the CRI clock source so we can get at the
6386 * display and the reference clock for VGA
6387 * hotplug / manual detection.
6388 */
6389 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6390 phy = DPIO_PHY0;
6391 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6392 DPLL_REFA_CLK_ENABLE_VLV);
6393 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6394 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6395 } else {
6396 phy = DPIO_PHY1;
6397 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6398 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6399 }
6400 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6401 vlv_set_power_well(dev_priv, power_well, true);
6402
6403 /* Poll for phypwrgood signal */
6404 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6405 DRM_ERROR("Display PHY %d is not power up\n", phy);
6406
6407 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6408 PHY_COM_LANE_RESET_DEASSERT(phy));
6409}
6410
6411static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6412 struct i915_power_well *power_well)
6413{
6414 enum dpio_phy phy;
6415
6416 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6417 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6418
6419 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6420 phy = DPIO_PHY0;
6421 assert_pll_disabled(dev_priv, PIPE_A);
6422 assert_pll_disabled(dev_priv, PIPE_B);
6423 } else {
6424 phy = DPIO_PHY1;
6425 assert_pll_disabled(dev_priv, PIPE_C);
6426 }
6427
6428 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6429 ~PHY_COM_LANE_RESET_DEASSERT(phy));
6430
6431 vlv_set_power_well(dev_priv, power_well, false);
6432}
6433
6434static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6435 struct i915_power_well *power_well)
6436{
6437 enum pipe pipe = power_well->data;
6438 bool enabled;
6439 u32 state, ctrl;
6440
6441 mutex_lock(&dev_priv->rps.hw_lock);
6442
6443 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6444 /*
6445 * We only ever set the power-on and power-gate states, anything
6446 * else is unexpected.
6447 */
6448 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6449 enabled = state == DP_SSS_PWR_ON(pipe);
6450
6451 /*
6452 * A transient state at this point would mean some unexpected party
6453 * is poking at the power controls too.
6454 */
6455 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6456 WARN_ON(ctrl << 16 != state);
6457
6458 mutex_unlock(&dev_priv->rps.hw_lock);
6459
6460 return enabled;
6461}
6462
6463static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6464 struct i915_power_well *power_well,
6465 bool enable)
6466{
6467 enum pipe pipe = power_well->data;
6468 u32 state;
6469 u32 ctrl;
6470
6471 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6472
6473 mutex_lock(&dev_priv->rps.hw_lock);
6474
6475#define COND \
6476 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6477
6478 if (COND)
6479 goto out;
6480
6481 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6482 ctrl &= ~DP_SSC_MASK(pipe);
6483 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6484 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6485
6486 if (wait_for(COND, 100))
6487 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6488 state,
6489 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6490
6491#undef COND
6492
6493out:
6494 mutex_unlock(&dev_priv->rps.hw_lock);
6495}
6496
6497static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6498 struct i915_power_well *power_well)
6499{
6500 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6501}
6502
6503static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6504 struct i915_power_well *power_well)
6505{
6506 WARN_ON_ONCE(power_well->data != PIPE_A &&
6507 power_well->data != PIPE_B &&
6508 power_well->data != PIPE_C);
6509
6510 chv_set_pipe_power_well(dev_priv, power_well, true);
6511}
6512
6513static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6514 struct i915_power_well *power_well)
6515{
6516 WARN_ON_ONCE(power_well->data != PIPE_A &&
6517 power_well->data != PIPE_B &&
6518 power_well->data != PIPE_C);
6519
6520 chv_set_pipe_power_well(dev_priv, power_well, false);
6521}
6522
6255static void check_power_well_state(struct drm_i915_private *dev_priv, 6523static void check_power_well_state(struct drm_i915_private *dev_priv,
6256 struct i915_power_well *power_well) 6524 struct i915_power_well *power_well)
6257{ 6525{
@@ -6443,6 +6711,39 @@ EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6443 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 6711 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6444 BIT(POWER_DOMAIN_INIT)) 6712 BIT(POWER_DOMAIN_INIT))
6445 6713
6714#define CHV_PIPE_A_POWER_DOMAINS ( \
6715 BIT(POWER_DOMAIN_PIPE_A) | \
6716 BIT(POWER_DOMAIN_INIT))
6717
6718#define CHV_PIPE_B_POWER_DOMAINS ( \
6719 BIT(POWER_DOMAIN_PIPE_B) | \
6720 BIT(POWER_DOMAIN_INIT))
6721
6722#define CHV_PIPE_C_POWER_DOMAINS ( \
6723 BIT(POWER_DOMAIN_PIPE_C) | \
6724 BIT(POWER_DOMAIN_INIT))
6725
6726#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6727 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6728 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6729 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6730 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6731 BIT(POWER_DOMAIN_INIT))
6732
6733#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6734 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6735 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6736 BIT(POWER_DOMAIN_INIT))
6737
6738#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6739 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6740 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6741 BIT(POWER_DOMAIN_INIT))
6742
6743#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6744 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6745 BIT(POWER_DOMAIN_INIT))
6746
6446static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 6747static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6447 .sync_hw = i9xx_always_on_power_well_noop, 6748 .sync_hw = i9xx_always_on_power_well_noop,
6448 .enable = i9xx_always_on_power_well_noop, 6749 .enable = i9xx_always_on_power_well_noop,
@@ -6450,6 +6751,20 @@ static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6450 .is_enabled = i9xx_always_on_power_well_enabled, 6751 .is_enabled = i9xx_always_on_power_well_enabled,
6451}; 6752};
6452 6753
6754static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6755 .sync_hw = chv_pipe_power_well_sync_hw,
6756 .enable = chv_pipe_power_well_enable,
6757 .disable = chv_pipe_power_well_disable,
6758 .is_enabled = chv_pipe_power_well_enabled,
6759};
6760
6761static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6762 .sync_hw = vlv_power_well_sync_hw,
6763 .enable = chv_dpio_cmn_power_well_enable,
6764 .disable = chv_dpio_cmn_power_well_disable,
6765 .is_enabled = vlv_power_well_enabled,
6766};
6767
6453static struct i915_power_well i9xx_always_on_power_well[] = { 6768static struct i915_power_well i9xx_always_on_power_well[] = {
6454 { 6769 {
6455 .name = "always-on", 6770 .name = "always-on",
@@ -6572,6 +6887,107 @@ static struct i915_power_well vlv_power_wells[] = {
6572 }, 6887 },
6573}; 6888};
6574 6889
6890static struct i915_power_well chv_power_wells[] = {
6891 {
6892 .name = "always-on",
6893 .always_on = 1,
6894 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6895 .ops = &i9xx_always_on_power_well_ops,
6896 },
6897#if 0
6898 {
6899 .name = "display",
6900 .domains = VLV_DISPLAY_POWER_DOMAINS,
6901 .data = PUNIT_POWER_WELL_DISP2D,
6902 .ops = &vlv_display_power_well_ops,
6903 },
6904 {
6905 .name = "pipe-a",
6906 .domains = CHV_PIPE_A_POWER_DOMAINS,
6907 .data = PIPE_A,
6908 .ops = &chv_pipe_power_well_ops,
6909 },
6910 {
6911 .name = "pipe-b",
6912 .domains = CHV_PIPE_B_POWER_DOMAINS,
6913 .data = PIPE_B,
6914 .ops = &chv_pipe_power_well_ops,
6915 },
6916 {
6917 .name = "pipe-c",
6918 .domains = CHV_PIPE_C_POWER_DOMAINS,
6919 .data = PIPE_C,
6920 .ops = &chv_pipe_power_well_ops,
6921 },
6922#endif
6923 {
6924 .name = "dpio-common-bc",
6925 /*
6926 * XXX: cmnreset for one PHY seems to disturb the other.
6927 * As a workaround keep both powered on at the same
6928 * time for now.
6929 */
6930 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
6931 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6932 .ops = &chv_dpio_cmn_power_well_ops,
6933 },
6934 {
6935 .name = "dpio-common-d",
6936 /*
6937 * XXX: cmnreset for one PHY seems to disturb the other.
6938 * As a workaround keep both powered on at the same
6939 * time for now.
6940 */
6941 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
6942 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
6943 .ops = &chv_dpio_cmn_power_well_ops,
6944 },
6945#if 0
6946 {
6947 .name = "dpio-tx-b-01",
6948 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6949 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6950 .ops = &vlv_dpio_power_well_ops,
6951 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6952 },
6953 {
6954 .name = "dpio-tx-b-23",
6955 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6956 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6957 .ops = &vlv_dpio_power_well_ops,
6958 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6959 },
6960 {
6961 .name = "dpio-tx-c-01",
6962 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6963 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6964 .ops = &vlv_dpio_power_well_ops,
6965 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6966 },
6967 {
6968 .name = "dpio-tx-c-23",
6969 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6970 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6971 .ops = &vlv_dpio_power_well_ops,
6972 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6973 },
6974 {
6975 .name = "dpio-tx-d-01",
6976 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6977 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6978 .ops = &vlv_dpio_power_well_ops,
6979 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
6980 },
6981 {
6982 .name = "dpio-tx-d-23",
6983 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6984 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6985 .ops = &vlv_dpio_power_well_ops,
6986 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
6987 },
6988#endif
6989};
6990
6575static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 6991static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6576 enum punit_power_well power_well_id) 6992 enum punit_power_well power_well_id)
6577{ 6993{
@@ -6608,6 +7024,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
6608 } else if (IS_BROADWELL(dev_priv->dev)) { 7024 } else if (IS_BROADWELL(dev_priv->dev)) {
6609 set_power_wells(power_domains, bdw_power_wells); 7025 set_power_wells(power_domains, bdw_power_wells);
6610 hsw_pwr = power_domains; 7026 hsw_pwr = power_domains;
7027 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7028 set_power_wells(power_domains, chv_power_wells);
6611 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 7029 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6612 set_power_wells(power_domains, vlv_power_wells); 7030 set_power_wells(power_domains, vlv_power_wells);
6613 } else { 7031 } else {
@@ -6835,11 +7253,13 @@ void intel_init_pm(struct drm_device *dev)
6835 else if (INTEL_INFO(dev)->gen == 8) 7253 else if (INTEL_INFO(dev)->gen == 8)
6836 dev_priv->display.init_clock_gating = gen8_init_clock_gating; 7254 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6837 } else if (IS_CHERRYVIEW(dev)) { 7255 } else if (IS_CHERRYVIEW(dev)) {
6838 dev_priv->display.update_wm = valleyview_update_wm; 7256 dev_priv->display.update_wm = cherryview_update_wm;
7257 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6839 dev_priv->display.init_clock_gating = 7258 dev_priv->display.init_clock_gating =
6840 cherryview_init_clock_gating; 7259 cherryview_init_clock_gating;
6841 } else if (IS_VALLEYVIEW(dev)) { 7260 } else if (IS_VALLEYVIEW(dev)) {
6842 dev_priv->display.update_wm = valleyview_update_wm; 7261 dev_priv->display.update_wm = valleyview_update_wm;
7262 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6843 dev_priv->display.init_clock_gating = 7263 dev_priv->display.init_clock_gating =
6844 valleyview_init_clock_gating; 7264 valleyview_init_clock_gating;
6845 } else if (IS_PINEVIEW(dev)) { 7265 } else if (IS_PINEVIEW(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 16371a444426..117543e58d48 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -476,8 +476,8 @@ static bool stop_ring(struct intel_engine_cs *ring)
476 476
477 if (!IS_GEN2(ring->dev)) { 477 if (!IS_GEN2(ring->dev)) {
478 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); 478 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
479 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { 479 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
480 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); 480 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
481 return false; 481 return false;
482 } 482 }
483 } 483 }
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 168c6652cda1..0bdb00b7c59c 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -53,6 +53,7 @@ static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl
53 enum pipe pipe = crtc->pipe; 53 enum pipe pipe = crtc->pipe;
54 long timeout = msecs_to_jiffies_timeout(1); 54 long timeout = msecs_to_jiffies_timeout(1);
55 int scanline, min, max, vblank_start; 55 int scanline, min, max, vblank_start;
56 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
56 DEFINE_WAIT(wait); 57 DEFINE_WAIT(wait);
57 58
58 WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex)); 59 WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex));
@@ -81,7 +82,7 @@ static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl
81 * other CPUs can see the task state update by the time we 82 * other CPUs can see the task state update by the time we
82 * read the scanline. 83 * read the scanline.
83 */ 84 */
84 prepare_to_wait(&crtc->vbl_wait, &wait, TASK_UNINTERRUPTIBLE); 85 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
85 86
86 scanline = intel_get_crtc_scanline(crtc); 87 scanline = intel_get_crtc_scanline(crtc);
87 if (scanline < min || scanline > max) 88 if (scanline < min || scanline > max)
@@ -100,7 +101,7 @@ static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl
100 local_irq_disable(); 101 local_irq_disable();
101 } 102 }
102 103
103 finish_wait(&crtc->vbl_wait, &wait); 104 finish_wait(wq, &wait);
104 105
105 drm_vblank_put(dev, pipe); 106 drm_vblank_put(dev, pipe);
106 107
@@ -163,6 +164,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
163 sprctl &= ~SP_PIXFORMAT_MASK; 164 sprctl &= ~SP_PIXFORMAT_MASK;
164 sprctl &= ~SP_YUV_BYTE_ORDER_MASK; 165 sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
165 sprctl &= ~SP_TILED; 166 sprctl &= ~SP_TILED;
167 sprctl &= ~SP_ROTATE_180;
166 168
167 switch (fb->pixel_format) { 169 switch (fb->pixel_format) {
168 case DRM_FORMAT_YUYV: 170 case DRM_FORMAT_YUYV:
@@ -235,6 +237,14 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
235 fb->pitches[0]); 237 fb->pitches[0]);
236 linear_offset -= sprsurf_offset; 238 linear_offset -= sprsurf_offset;
237 239
240 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
241 sprctl |= SP_ROTATE_180;
242
243 x += src_w;
244 y += src_h;
245 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
246 }
247
238 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); 248 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
239 249
240 intel_update_primary_plane(intel_crtc); 250 intel_update_primary_plane(intel_crtc);
@@ -364,6 +374,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
364 sprctl &= ~SPRITE_RGB_ORDER_RGBX; 374 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
365 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; 375 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
366 sprctl &= ~SPRITE_TILED; 376 sprctl &= ~SPRITE_TILED;
377 sprctl &= ~SPRITE_ROTATE_180;
367 378
368 switch (fb->pixel_format) { 379 switch (fb->pixel_format) {
369 case DRM_FORMAT_XBGR8888: 380 case DRM_FORMAT_XBGR8888:
@@ -426,6 +437,18 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
426 pixel_size, fb->pitches[0]); 437 pixel_size, fb->pitches[0]);
427 linear_offset -= sprsurf_offset; 438 linear_offset -= sprsurf_offset;
428 439
440 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
441 sprctl |= SPRITE_ROTATE_180;
442
443 /* HSW and BDW does this automagically in hardware */
444 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
445 x += src_w;
446 y += src_h;
447 linear_offset += src_h * fb->pitches[0] +
448 src_w * pixel_size;
449 }
450 }
451
429 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); 452 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
430 453
431 intel_update_primary_plane(intel_crtc); 454 intel_update_primary_plane(intel_crtc);
@@ -571,6 +594,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
571 dvscntr &= ~DVS_RGB_ORDER_XBGR; 594 dvscntr &= ~DVS_RGB_ORDER_XBGR;
572 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; 595 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
573 dvscntr &= ~DVS_TILED; 596 dvscntr &= ~DVS_TILED;
597 dvscntr &= ~DVS_ROTATE_180;
574 598
575 switch (fb->pixel_format) { 599 switch (fb->pixel_format) {
576 case DRM_FORMAT_XBGR8888: 600 case DRM_FORMAT_XBGR8888:
@@ -628,6 +652,14 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
628 pixel_size, fb->pitches[0]); 652 pixel_size, fb->pitches[0]);
629 linear_offset -= dvssurf_offset; 653 linear_offset -= dvssurf_offset;
630 654
655 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
656 dvscntr |= DVS_ROTATE_180;
657
658 x += src_w;
659 y += src_h;
660 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
661 }
662
631 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); 663 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
632 664
633 intel_update_primary_plane(intel_crtc); 665 intel_update_primary_plane(intel_crtc);
@@ -895,6 +927,9 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
895 max_scale = intel_plane->max_downscale << 16; 927 max_scale = intel_plane->max_downscale << 16;
896 min_scale = intel_plane->can_scale ? 1 : (1 << 16); 928 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
897 929
930 drm_rect_rotate(&src, fb->width << 16, fb->height << 16,
931 intel_plane->rotation);
932
898 hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale); 933 hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
899 BUG_ON(hscale < 0); 934 BUG_ON(hscale < 0);
900 935
@@ -933,6 +968,9 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
933 drm_rect_width(&dst) * hscale - drm_rect_width(&src), 968 drm_rect_width(&dst) * hscale - drm_rect_width(&src),
934 drm_rect_height(&dst) * vscale - drm_rect_height(&src)); 969 drm_rect_height(&dst) * vscale - drm_rect_height(&src));
935 970
971 drm_rect_rotate_inv(&src, fb->width << 16, fb->height << 16,
972 intel_plane->rotation);
973
936 /* sanity check to make sure the src viewport wasn't enlarged */ 974 /* sanity check to make sure the src viewport wasn't enlarged */
937 WARN_ON(src.x1 < (int) src_x || 975 WARN_ON(src.x1 < (int) src_x ||
938 src.y1 < (int) src_y || 976 src.y1 < (int) src_y ||
@@ -1180,18 +1218,42 @@ out_unlock:
1180 return ret; 1218 return ret;
1181} 1219}
1182 1220
1183void intel_plane_restore(struct drm_plane *plane) 1221static int intel_plane_set_property(struct drm_plane *plane,
1222 struct drm_property *prop,
1223 uint64_t val)
1224{
1225 struct drm_device *dev = plane->dev;
1226 struct intel_plane *intel_plane = to_intel_plane(plane);
1227 uint64_t old_val;
1228 int ret = -ENOENT;
1229
1230 if (prop == dev->mode_config.rotation_property) {
1231 /* exactly one rotation angle please */
1232 if (hweight32(val & 0xf) != 1)
1233 return -EINVAL;
1234
1235 old_val = intel_plane->rotation;
1236 intel_plane->rotation = val;
1237 ret = intel_plane_restore(plane);
1238 if (ret)
1239 intel_plane->rotation = old_val;
1240 }
1241
1242 return ret;
1243}
1244
1245int intel_plane_restore(struct drm_plane *plane)
1184{ 1246{
1185 struct intel_plane *intel_plane = to_intel_plane(plane); 1247 struct intel_plane *intel_plane = to_intel_plane(plane);
1186 1248
1187 if (!plane->crtc || !plane->fb) 1249 if (!plane->crtc || !plane->fb)
1188 return; 1250 return 0;
1189 1251
1190 intel_update_plane(plane, plane->crtc, plane->fb, 1252 return intel_update_plane(plane, plane->crtc, plane->fb,
1191 intel_plane->crtc_x, intel_plane->crtc_y, 1253 intel_plane->crtc_x, intel_plane->crtc_y,
1192 intel_plane->crtc_w, intel_plane->crtc_h, 1254 intel_plane->crtc_w, intel_plane->crtc_h,
1193 intel_plane->src_x, intel_plane->src_y, 1255 intel_plane->src_x, intel_plane->src_y,
1194 intel_plane->src_w, intel_plane->src_h); 1256 intel_plane->src_w, intel_plane->src_h);
1195} 1257}
1196 1258
1197void intel_plane_disable(struct drm_plane *plane) 1259void intel_plane_disable(struct drm_plane *plane)
@@ -1206,6 +1268,7 @@ static const struct drm_plane_funcs intel_plane_funcs = {
1206 .update_plane = intel_update_plane, 1268 .update_plane = intel_update_plane,
1207 .disable_plane = intel_disable_plane, 1269 .disable_plane = intel_disable_plane,
1208 .destroy = intel_destroy_plane, 1270 .destroy = intel_destroy_plane,
1271 .set_property = intel_plane_set_property,
1209}; 1272};
1210 1273
1211static uint32_t ilk_plane_formats[] = { 1274static uint32_t ilk_plane_formats[] = {
@@ -1310,13 +1373,28 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1310 1373
1311 intel_plane->pipe = pipe; 1374 intel_plane->pipe = pipe;
1312 intel_plane->plane = plane; 1375 intel_plane->plane = plane;
1376 intel_plane->rotation = BIT(DRM_ROTATE_0);
1313 possible_crtcs = (1 << pipe); 1377 possible_crtcs = (1 << pipe);
1314 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, 1378 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
1315 &intel_plane_funcs, 1379 &intel_plane_funcs,
1316 plane_formats, num_plane_formats, 1380 plane_formats, num_plane_formats,
1317 false); 1381 false);
1318 if (ret) 1382 if (ret) {
1319 kfree(intel_plane); 1383 kfree(intel_plane);
1384 goto out;
1385 }
1386
1387 if (!dev->mode_config.rotation_property)
1388 dev->mode_config.rotation_property =
1389 drm_mode_create_rotation_property(dev,
1390 BIT(DRM_ROTATE_0) |
1391 BIT(DRM_ROTATE_180));
1392
1393 if (dev->mode_config.rotation_property)
1394 drm_object_attach_property(&intel_plane->base.base,
1395 dev->mode_config.rotation_property,
1396 intel_plane->rotation);
1320 1397
1398 out:
1321 return ret; 1399 return ret;
1322} 1400}
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index d2f64b9ccefd..6b4fbf3a3263 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1313,6 +1313,17 @@ extern int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
1313extern void drm_calc_timestamping_constants(struct drm_crtc *crtc, 1313extern void drm_calc_timestamping_constants(struct drm_crtc *crtc,
1314 const struct drm_display_mode *mode); 1314 const struct drm_display_mode *mode);
1315 1315
1316/**
1317 * drm_crtc_vblank_waitqueue - get vblank waitqueue for the CRTC
1318 * @crtc: which CRTC's vblank waitqueue to retrieve
1319 *
1320 * This function returns a pointer to the vblank waitqueue for the CRTC.
1321 * Drivers can use this to implement vblank waits using wait_event() & co.
1322 */
1323static inline wait_queue_head_t *drm_crtc_vblank_waitqueue(struct drm_crtc *crtc)
1324{
1325 return &crtc->dev->vblank[drm_crtc_index(crtc)].queue;
1326}
1316 1327
1317/* Modesetting support */ 1328/* Modesetting support */
1318extern void drm_vblank_pre_modeset(struct drm_device *dev, int crtc); 1329extern void drm_vblank_pre_modeset(struct drm_device *dev, int crtc);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 2c1f58d6957a..0375d75552f1 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -825,6 +825,7 @@ struct drm_mode_config {
825 struct drm_property *dpms_property; 825 struct drm_property *dpms_property;
826 struct drm_property *path_property; 826 struct drm_property *path_property;
827 struct drm_property *plane_type_property; 827 struct drm_property *plane_type_property;
828 struct drm_property *rotation_property;
828 829
829 /* DVI-I properties */ 830 /* DVI-I properties */
830 struct drm_property *dvi_i_subconnector_property; 831 struct drm_property *dvi_i_subconnector_property;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 01:48:10 -0400