diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2013-05-14 02:34:54 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2013-06-30 23:43:21 -0400 |
commit | d53635a980a37f1bb2d49032b31a25a3b0d49fb0 (patch) | |
tree | a7f5e82a5997116ea0705897cba6414f25acf4cc | |
parent | 9e895ace5d82df8929b16f58e9f515f6d54ab82d (diff) |
drm/nouveau: pull in latest ucode builds from external tree
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
5 files changed, 51 insertions, 48 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h index c92520f3ed46..241b27201206 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h | |||
@@ -1,4 +1,4 @@ | |||
1 | static u32 nva3_pcopy_data[] = { | 1 | uint32_t nva3_pcopy_data[] = { |
2 | /* 0x0000: ctx_object */ | 2 | /* 0x0000: ctx_object */ |
3 | 0x00000000, | 3 | 0x00000000, |
4 | /* 0x0004: ctx_dma */ | 4 | /* 0x0004: ctx_dma */ |
@@ -183,7 +183,7 @@ static u32 nva3_pcopy_data[] = { | |||
183 | 0x00000800, | 183 | 0x00000800, |
184 | }; | 184 | }; |
185 | 185 | ||
186 | static u32 nva3_pcopy_code[] = { | 186 | uint32_t nva3_pcopy_code[] = { |
187 | /* 0x0000: main */ | 187 | /* 0x0000: main */ |
188 | 0x04fe04bd, | 188 | 0x04fe04bd, |
189 | 0x3517f000, | 189 | 0x3517f000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h index 0d98c6c0958d..98cc4216a372 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h | |||
@@ -1,4 +1,4 @@ | |||
1 | static u32 nvc0_pcopy_data[] = { | 1 | uint32_t nvc0_pcopy_data[] = { |
2 | /* 0x0000: ctx_object */ | 2 | /* 0x0000: ctx_object */ |
3 | 0x00000000, | 3 | 0x00000000, |
4 | /* 0x0004: ctx_query_address_high */ | 4 | /* 0x0004: ctx_query_address_high */ |
@@ -171,7 +171,7 @@ static u32 nvc0_pcopy_data[] = { | |||
171 | 0x00000800, | 171 | 0x00000800, |
172 | }; | 172 | }; |
173 | 173 | ||
174 | static u32 nvc0_pcopy_code[] = { | 174 | uint32_t nvc0_pcopy_code[] = { |
175 | /* 0x0000: main */ | 175 | /* 0x0000: main */ |
176 | 0x04fe04bd, | 176 | 0x04fe04bd, |
177 | 0x3517f000, | 177 | 0x3517f000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h b/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h index 09962e4210e9..38676c74e6e0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h | |||
@@ -1,4 +1,4 @@ | |||
1 | static uint32_t nv98_pcrypt_data[] = { | 1 | uint32_t nv98_pcrypt_data[] = { |
2 | /* 0x0000: ctx_dma */ | 2 | /* 0x0000: ctx_dma */ |
3 | /* 0x0000: ctx_dma_query */ | 3 | /* 0x0000: ctx_dma_query */ |
4 | 0x00000000, | 4 | 0x00000000, |
@@ -150,7 +150,7 @@ static uint32_t nv98_pcrypt_data[] = { | |||
150 | 0x00000000, | 150 | 0x00000000, |
151 | }; | 151 | }; |
152 | 152 | ||
153 | static uint32_t nv98_pcrypt_code[] = { | 153 | uint32_t nv98_pcrypt_code[] = { |
154 | 0x17f004bd, | 154 | 0x17f004bd, |
155 | 0x0010fe35, | 155 | 0x0010fe35, |
156 | 0xf10004fe, | 156 | 0xf10004fe, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h index 96050ddb22ca..a9711712de57 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h | |||
@@ -34,31 +34,34 @@ uint32_t nvc0_grgpc_data[] = { | |||
34 | 0x00000000, | 34 | 0x00000000, |
35 | /* 0x0064: chipsets */ | 35 | /* 0x0064: chipsets */ |
36 | 0x000000c0, | 36 | 0x000000c0, |
37 | 0x012800c8, | 37 | 0x013400d4, |
38 | 0x01e40194, | 38 | 0x01f001a0, |
39 | 0x000000c1, | 39 | 0x000000c1, |
40 | 0x012c00c8, | 40 | 0x013800d4, |
41 | 0x01f80194, | 41 | 0x020401a0, |
42 | 0x000000c3, | 42 | 0x000000c3, |
43 | 0x012800c8, | 43 | 0x013400d4, |
44 | 0x01f40194, | 44 | 0x020001a0, |
45 | 0x000000c4, | 45 | 0x000000c4, |
46 | 0x012800c8, | 46 | 0x013400d4, |
47 | 0x01f40194, | 47 | 0x020001a0, |
48 | 0x000000c8, | 48 | 0x000000c8, |
49 | 0x012800c8, | 49 | 0x013400d4, |
50 | 0x01e40194, | 50 | 0x01f001a0, |
51 | 0x000000ce, | 51 | 0x000000ce, |
52 | 0x012800c8, | 52 | 0x013400d4, |
53 | 0x01f40194, | 53 | 0x020001a0, |
54 | 0x000000cf, | 54 | 0x000000cf, |
55 | 0x012800c8, | 55 | 0x013400d4, |
56 | 0x01f00194, | 56 | 0x01fc01a0, |
57 | 0x000000d9, | 57 | 0x000000d9, |
58 | 0x0194012c, | 58 | 0x01a00138, |
59 | 0x025401f8, | 59 | 0x02600204, |
60 | 0x000000d7, | ||
61 | 0x01a00138, | ||
62 | 0x02600204, | ||
60 | 0x00000000, | 63 | 0x00000000, |
61 | /* 0x00c8: nvc0_gpc_mmio_head */ | 64 | /* 0x00d4: nvc0_gpc_mmio_head */ |
62 | 0x00000380, | 65 | 0x00000380, |
63 | 0x14000400, | 66 | 0x14000400, |
64 | 0x20000450, | 67 | 0x20000450, |
@@ -83,10 +86,10 @@ uint32_t nvc0_grgpc_data[] = { | |||
83 | 0x00000c8c, | 86 | 0x00000c8c, |
84 | 0x08001000, | 87 | 0x08001000, |
85 | 0x00001014, | 88 | 0x00001014, |
86 | /* 0x0128: nvc0_gpc_mmio_tail */ | 89 | /* 0x0134: nvc0_gpc_mmio_tail */ |
87 | 0x00000c6c, | 90 | 0x00000c6c, |
88 | /* 0x012c: nvc1_gpc_mmio_tail */ | 91 | /* 0x0138: nvc1_gpc_mmio_tail */ |
89 | /* 0x012c: nvd9_gpc_mmio_head */ | 92 | /* 0x0138: nvd9_gpc_mmio_head */ |
90 | 0x00000380, | 93 | 0x00000380, |
91 | 0x04000400, | 94 | 0x04000400, |
92 | 0x0800040c, | 95 | 0x0800040c, |
@@ -113,8 +116,8 @@ uint32_t nvc0_grgpc_data[] = { | |||
113 | 0x00000c8c, | 116 | 0x00000c8c, |
114 | 0x08001000, | 117 | 0x08001000, |
115 | 0x00001014, | 118 | 0x00001014, |
116 | /* 0x0194: nvd9_gpc_mmio_tail */ | 119 | /* 0x01a0: nvd9_gpc_mmio_tail */ |
117 | /* 0x0194: nvc0_tpc_mmio_head */ | 120 | /* 0x01a0: nvc0_tpc_mmio_head */ |
118 | 0x00000018, | 121 | 0x00000018, |
119 | 0x0000003c, | 122 | 0x0000003c, |
120 | 0x00000048, | 123 | 0x00000048, |
@@ -135,16 +138,16 @@ uint32_t nvc0_grgpc_data[] = { | |||
135 | 0x4c000644, | 138 | 0x4c000644, |
136 | 0x00000698, | 139 | 0x00000698, |
137 | 0x04000750, | 140 | 0x04000750, |
138 | /* 0x01e4: nvc0_tpc_mmio_tail */ | 141 | /* 0x01f0: nvc0_tpc_mmio_tail */ |
139 | 0x00000758, | 142 | 0x00000758, |
140 | 0x000002c4, | 143 | 0x000002c4, |
141 | 0x000006e0, | 144 | 0x000006e0, |
142 | /* 0x01f0: nvcf_tpc_mmio_tail */ | 145 | /* 0x01fc: nvcf_tpc_mmio_tail */ |
143 | 0x000004bc, | 146 | 0x000004bc, |
144 | /* 0x01f4: nvc3_tpc_mmio_tail */ | 147 | /* 0x0200: nvc3_tpc_mmio_tail */ |
145 | 0x00000544, | 148 | 0x00000544, |
146 | /* 0x01f8: nvc1_tpc_mmio_tail */ | 149 | /* 0x0204: nvc1_tpc_mmio_tail */ |
147 | /* 0x01f8: nvd9_tpc_mmio_head */ | 150 | /* 0x0204: nvd9_tpc_mmio_head */ |
148 | 0x00000018, | 151 | 0x00000018, |
149 | 0x0000003c, | 152 | 0x0000003c, |
150 | 0x00000048, | 153 | 0x00000048, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h index bb03d2a1d57b..b655117e8dac 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h | |||
@@ -30,23 +30,25 @@ uint32_t nvc0_grhub_data[] = { | |||
30 | 0x00000000, | 30 | 0x00000000, |
31 | /* 0x005c: chipsets */ | 31 | /* 0x005c: chipsets */ |
32 | 0x000000c0, | 32 | 0x000000c0, |
33 | 0x013c00a0, | 33 | 0x014400a8, |
34 | 0x000000c1, | 34 | 0x000000c1, |
35 | 0x014000a0, | 35 | 0x014800a8, |
36 | 0x000000c3, | 36 | 0x000000c3, |
37 | 0x013c00a0, | 37 | 0x014400a8, |
38 | 0x000000c4, | 38 | 0x000000c4, |
39 | 0x013c00a0, | 39 | 0x014400a8, |
40 | 0x000000c8, | 40 | 0x000000c8, |
41 | 0x013c00a0, | 41 | 0x014400a8, |
42 | 0x000000ce, | 42 | 0x000000ce, |
43 | 0x013c00a0, | 43 | 0x014400a8, |
44 | 0x000000cf, | 44 | 0x000000cf, |
45 | 0x013c00a0, | 45 | 0x014400a8, |
46 | 0x000000d9, | 46 | 0x000000d9, |
47 | 0x01dc0140, | 47 | 0x01e40148, |
48 | 0x000000d7, | ||
49 | 0x01e40148, | ||
48 | 0x00000000, | 50 | 0x00000000, |
49 | /* 0x00a0: nvc0_hub_mmio_head */ | 51 | /* 0x00a8: nvc0_hub_mmio_head */ |
50 | 0x0417e91c, | 52 | 0x0417e91c, |
51 | 0x04400204, | 53 | 0x04400204, |
52 | 0x28404004, | 54 | 0x28404004, |
@@ -86,10 +88,10 @@ uint32_t nvc0_grhub_data[] = { | |||
86 | 0x08408800, | 88 | 0x08408800, |
87 | 0x0c408900, | 89 | 0x0c408900, |
88 | 0x00408980, | 90 | 0x00408980, |
89 | /* 0x013c: nvc0_hub_mmio_tail */ | 91 | /* 0x0144: nvc0_hub_mmio_tail */ |
90 | 0x044064c0, | 92 | 0x044064c0, |
91 | /* 0x0140: nvc1_hub_mmio_tail */ | 93 | /* 0x0148: nvc1_hub_mmio_tail */ |
92 | /* 0x0140: nvd9_hub_mmio_head */ | 94 | /* 0x0148: nvd9_hub_mmio_head */ |
93 | 0x0417e91c, | 95 | 0x0417e91c, |
94 | 0x04400204, | 96 | 0x04400204, |
95 | 0x24404004, | 97 | 0x24404004, |
@@ -129,9 +131,7 @@ uint32_t nvc0_grhub_data[] = { | |||
129 | 0x08408800, | 131 | 0x08408800, |
130 | 0x0c408900, | 132 | 0x0c408900, |
131 | 0x00408980, | 133 | 0x00408980, |
132 | /* 0x01dc: nvd9_hub_mmio_tail */ | 134 | /* 0x01e4: nvd9_hub_mmio_tail */ |
133 | 0x00000000, | ||
134 | 0x00000000, | ||
135 | 0x00000000, | 135 | 0x00000000, |
136 | 0x00000000, | 136 | 0x00000000, |
137 | 0x00000000, | 137 | 0x00000000, |