dmaengine: qcom_bam_dma: Add support for BAM v1.7.0

Add register offset table entry for the newer (v1.7.0) version of the BAM IP
found on MSM8916. Update the DT bindings documentation.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

2 files changed, 31 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
index f8c3311b7153..1c9d48ea4914 100644
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible: must be one of the following:
  * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
  * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
+ * "qcom,bam-v1.7.0" for MSM8916
 - reg: Address range for DMA registers
 - interrupts: Should contain the one interrupt shared by all channels
 - #dma-cells: must be <1>, the cell in the dmas property of the client device
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index cbacee55f7ef..1576cd97d4d8 100644
--- a/drivers/dma/qcom_bam_dma.c
+++ b/drivers/dma/qcom_bam_dma.c
@@ -171,6 +171,35 @@ static const struct reg_offset_data bam_v1_4_reg_info[] = {
         [BAM_P_FIFO_SIZES]      = { 0x1820, 0x00, 0x1000, 0x00 },
 };
 
+static const struct reg_offset_data bam_v1_7_reg_info[] = {
+        [BAM_CTRL]              = { 0x00000, 0x00, 0x00, 0x00 },
+        [BAM_REVISION]          = { 0x01000, 0x00, 0x00, 0x00 },
+        [BAM_NUM_PIPES]         = { 0x01008, 0x00, 0x00, 0x00 },
+        [BAM_DESC_CNT_TRSHLD]   = { 0x00008, 0x00, 0x00, 0x00 },
+        [BAM_IRQ_SRCS]          = { 0x03010, 0x00, 0x00, 0x00 },
+        [BAM_IRQ_SRCS_MSK]      = { 0x03014, 0x00, 0x00, 0x00 },
+        [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 },
+        [BAM_IRQ_STTS]          = { 0x00014, 0x00, 0x00, 0x00 },
+        [BAM_IRQ_CLR]           = { 0x00018, 0x00, 0x00, 0x00 },
+        [BAM_IRQ_EN]            = { 0x0001C, 0x00, 0x00, 0x00 },
+        [BAM_CNFG_BITS]         = { 0x0007C, 0x00, 0x00, 0x00 },
+        [BAM_IRQ_SRCS_EE]       = { 0x03000, 0x00, 0x00, 0x1000 },
+        [BAM_IRQ_SRCS_MSK_EE]   = { 0x03004, 0x00, 0x00, 0x1000 },
+        [BAM_P_CTRL]            = { 0x13000, 0x1000, 0x00, 0x00 },
+        [BAM_P_RST]             = { 0x13004, 0x1000, 0x00, 0x00 },
+        [BAM_P_HALT]            = { 0x13008, 0x1000, 0x00, 0x00 },
+        [BAM_P_IRQ_STTS]        = { 0x13010, 0x1000, 0x00, 0x00 },
+        [BAM_P_IRQ_CLR]         = { 0x13014, 0x1000, 0x00, 0x00 },
+        [BAM_P_IRQ_EN]          = { 0x13018, 0x1000, 0x00, 0x00 },
+        [BAM_P_EVNT_DEST_ADDR]  = { 0x1382C, 0x00, 0x1000, 0x00 },
+        [BAM_P_EVNT_REG]        = { 0x13818, 0x00, 0x1000, 0x00 },
+        [BAM_P_SW_OFSTS]        = { 0x13800, 0x00, 0x1000, 0x00 },
+        [BAM_P_DATA_FIFO_ADDR]  = { 0x13824, 0x00, 0x1000, 0x00 },
+        [BAM_P_DESC_FIFO_ADDR]  = { 0x1381C, 0x00, 0x1000, 0x00 },
+        [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 },
+        [BAM_P_FIFO_SIZES]      = { 0x13820, 0x00, 0x1000, 0x00 },
+};
+
 /* BAM CTRL */
 #define BAM_SW_RST                      BIT(0)
 #define BAM_EN                          BIT(1)
@@ -1051,6 +1080,7 @@ static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
 static const struct of_device_id bam_of_match[] = {
         { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
         { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
+        { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info },
         {}
 };