drm/i915: fix lane bandwidth capping for DP 1.2 sinks

DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which
the driver will treat as an invalid value and use 1.62Gbps instead. Fix
this by capping to 2.7Gbps for sinks reporting a 5.4Gbps max bw.

Also add a warning for reserved values.

v2:
- allow only bw values explicitly listed in the DP standard (Daniel,
  Chris)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 5 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b73971234013..26e162bb3a51 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -75,7 +75,12 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
         case DP_LINK_BW_1_62:
         case DP_LINK_BW_2_7:
                 break;
+        case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
+                max_link_bw = DP_LINK_BW_2_7;
+                break;
         default:
+                WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
+                     max_link_bw);
                 max_link_bw = DP_LINK_BW_1_62;
                 break;
         }