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authorBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>2014-07-31 13:11:00 -0400
committerEduardo Valentin <edubezval@gmail.com>2014-11-02 22:02:47 -0500
commitd37761ecde5f151f4748309fedaa1db53832cc2c (patch)
tree5b36937060964bb1dbb3975ff368b599fcf1f669
parente841971628fa355358ea6c5b0595eed0a6202595 (diff)
thermal: exynos: remove dead code for HW_MODE calibration
The commit 1928457 ("thermal: exynos: Add hardware mode thermal calibration support") has added HW_MODE feature but it has never been enabled. As such it has been a dead code for over a year now and should be removed from the kernel. We don't keep the unused/untested features in the kernel just in case that some future hardware might need it. Such code has a real maintainance cost (all other code changes have to take the dead code into account) and usually makes future changes more difficult, not easier (i.e. recent additions of Exynos5420 SoC and Exynos5260 SoC thermal support has not made use of any of the driver's currently unused/untested features, moreover the recently added code is more complex than needed because of the existing dead code). Also all removed dead code is still accessible in the kernel git repository and can be easily brought back if/when needed. There should be no functional changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
-rw-r--r--drivers/thermal/samsung/exynos_tmu.c33
-rw-r--r--drivers/thermal/samsung/exynos_tmu.h13
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.c3
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.h2
4 files changed, 1 insertions, 50 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index acbff14da3a4..4a55f112cc67 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -77,9 +77,6 @@ static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
77 struct exynos_tmu_platform_data *pdata = data->pdata; 77 struct exynos_tmu_platform_data *pdata = data->pdata;
78 int temp_code; 78 int temp_code;
79 79
80 if (pdata->cal_mode == HW_MODE)
81 return temp;
82
83 if (data->soc == SOC_ARCH_EXYNOS4210) 80 if (data->soc == SOC_ARCH_EXYNOS4210)
84 /* temp should range between 25 and 125 */ 81 /* temp should range between 25 and 125 */
85 if (temp < 25 || temp > 125) { 82 if (temp < 25 || temp > 125) {
@@ -114,9 +111,6 @@ static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
114 struct exynos_tmu_platform_data *pdata = data->pdata; 111 struct exynos_tmu_platform_data *pdata = data->pdata;
115 int temp; 112 int temp;
116 113
117 if (pdata->cal_mode == HW_MODE)
118 return temp_code;
119
120 if (data->soc == SOC_ARCH_EXYNOS4210) 114 if (data->soc == SOC_ARCH_EXYNOS4210)
121 /* temp_code should range between 75 and 175 */ 115 /* temp_code should range between 75 and 175 */
122 if (temp_code < 75 || temp_code > 175) { 116 if (temp_code < 75 || temp_code > 175) {
@@ -167,9 +161,6 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
167 if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) 161 if (TMU_SUPPORTS(pdata, TRIM_RELOAD))
168 __raw_writel(1, data->base + reg->triminfo_ctrl); 162 __raw_writel(1, data->base + reg->triminfo_ctrl);
169 163
170 if (pdata->cal_mode == HW_MODE)
171 goto skip_calib_data;
172
173 /* Save trimming info in order to perform calibration */ 164 /* Save trimming info in order to perform calibration */
174 if (data->soc == SOC_ARCH_EXYNOS5440) { 165 if (data->soc == SOC_ARCH_EXYNOS5440) {
175 /* 166 /*
@@ -210,7 +201,6 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
210 (pdata->efuse_value >> reg->triminfo_85_shift) & 201 (pdata->efuse_value >> reg->triminfo_85_shift) &
211 EXYNOS_TMU_TEMP_MASK; 202 EXYNOS_TMU_TEMP_MASK;
212 203
213skip_calib_data:
214 if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) { 204 if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) {
215 dev_err(&pdev->dev, "Invalid max trigger level\n"); 205 dev_err(&pdev->dev, "Invalid max trigger level\n");
216 ret = -EINVAL; 206 ret = -EINVAL;
@@ -325,7 +315,7 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
325 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 315 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
326 struct exynos_tmu_platform_data *pdata = data->pdata; 316 struct exynos_tmu_platform_data *pdata = data->pdata;
327 const struct exynos_tmu_registers *reg = pdata->registers; 317 const struct exynos_tmu_registers *reg = pdata->registers;
328 unsigned int con, interrupt_en, cal_val; 318 unsigned int con, interrupt_en;
329 319
330 mutex_lock(&data->lock); 320 mutex_lock(&data->lock);
331 clk_enable(data->clk); 321 clk_enable(data->clk);
@@ -351,27 +341,6 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
351 con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift); 341 con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
352 } 342 }
353 343
354 if (pdata->cal_mode == HW_MODE) {
355 con &= ~(reg->calib_mode_mask << reg->calib_mode_shift);
356 cal_val = 0;
357 switch (pdata->cal_type) {
358 case TYPE_TWO_POINT_TRIMMING:
359 cal_val = 3;
360 break;
361 case TYPE_ONE_POINT_TRIMMING_85:
362 cal_val = 2;
363 break;
364 case TYPE_ONE_POINT_TRIMMING_25:
365 cal_val = 1;
366 break;
367 case TYPE_NONE:
368 break;
369 default:
370 dev_err(&pdev->dev, "Invalid calibration type, using none\n");
371 }
372 con |= cal_val << reg->calib_mode_shift;
373 }
374
375 if (on) { 344 if (on) {
376 con |= (1 << reg->core_en_shift); 345 con |= (1 << reg->core_en_shift);
377 interrupt_en = 346 interrupt_en =
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 44ca6337e945..789a8f70f45c 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -34,11 +34,6 @@ enum calibration_type {
34 TYPE_NONE, 34 TYPE_NONE,
35}; 35};
36 36
37enum calibration_mode {
38 SW_MODE,
39 HW_MODE,
40};
41
42enum soc_type { 37enum soc_type {
43 SOC_ARCH_EXYNOS3250 = 1, 38 SOC_ARCH_EXYNOS3250 = 1,
44 SOC_ARCH_EXYNOS4210, 39 SOC_ARCH_EXYNOS4210,
@@ -95,10 +90,6 @@ enum soc_type {
95 * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl 90 * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
96 register. 91 register.
97 * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register. 92 * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
98 * @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl
99 register.
100 * @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl
101 register.
102 * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register. 93 * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
103 * @tmu_status: register drescribing the TMU status. 94 * @tmu_status: register drescribing the TMU status.
104 * @tmu_cur_temp: register containing the current temperature of the TMU. 95 * @tmu_cur_temp: register containing the current temperature of the TMU.
@@ -143,8 +134,6 @@ struct exynos_tmu_registers {
143 u32 therm_trip_en_shift; 134 u32 therm_trip_en_shift;
144 u32 buf_slope_sel_shift; 135 u32 buf_slope_sel_shift;
145 u32 buf_slope_sel_mask; 136 u32 buf_slope_sel_mask;
146 u32 calib_mode_shift;
147 u32 calib_mode_mask;
148 u32 core_en_shift; 137 u32 core_en_shift;
149 138
150 u32 tmu_status; 139 u32 tmu_status;
@@ -226,7 +215,6 @@ struct exynos_tmu_registers {
226 * @default_temp_offset: default temperature offset in case of no trimming 215 * @default_temp_offset: default temperature offset in case of no trimming
227 * @test_mux; information if SoC supports test MUX 216 * @test_mux; information if SoC supports test MUX
228 * @cal_type: calibration type for temperature 217 * @cal_type: calibration type for temperature
229 * @cal_mode: calibration mode for temperature
230 * @freq_clip_table: Table representing frequency reduction percentage. 218 * @freq_clip_table: Table representing frequency reduction percentage.
231 * @freq_tab_count: Count of the above table as frequency reduction may 219 * @freq_tab_count: Count of the above table as frequency reduction may
232 * applicable to only some of the trigger levels. 220 * applicable to only some of the trigger levels.
@@ -257,7 +245,6 @@ struct exynos_tmu_platform_data {
257 u8 test_mux; 245 u8 test_mux;
258 246
259 enum calibration_type cal_type; 247 enum calibration_type cal_type;
260 enum calibration_mode cal_mode;
261 enum soc_type type; 248 enum soc_type type;
262 struct freq_clip_table freq_tab[4]; 249 struct freq_clip_table freq_tab[4];
263 unsigned int freq_tab_count; 250 unsigned int freq_tab_count;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index d5cdfe524a3a..1d05bf8235aa 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -482,8 +482,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
482 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT, 482 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
483 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT, 483 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
484 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK, 484 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
485 .calib_mode_shift = EXYNOS_TMU_CALIB_MODE_SHIFT,
486 .calib_mode_mask = EXYNOS_TMU_CALIB_MODE_MASK,
487 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT, 485 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
488 .tmu_status = EXYNOS5440_TMU_S0_7_STATUS, 486 .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
489 .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP, 487 .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
@@ -520,7 +518,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
520 .reference_voltage = 16, \ 518 .reference_voltage = 16, \
521 .noise_cancel_mode = 4, \ 519 .noise_cancel_mode = 4, \
522 .cal_type = TYPE_ONE_POINT_TRIMMING, \ 520 .cal_type = TYPE_ONE_POINT_TRIMMING, \
523 .cal_mode = 0, \
524 .efuse_value = 0x5b2d, \ 521 .efuse_value = 0x5b2d, \
525 .min_efuse_value = 16, \ 522 .min_efuse_value = 16, \
526 .max_efuse_value = 76, \ 523 .max_efuse_value = 76, \
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index 9337c5a36167..ac03b76c51cc 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -62,8 +62,6 @@
62#define EXYNOS_TMU_TRIP_MODE_SHIFT 13 62#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
63#define EXYNOS_TMU_TRIP_MODE_MASK 0x7 63#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
64#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 64#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
65#define EXYNOS_TMU_CALIB_MODE_SHIFT 4
66#define EXYNOS_TMU_CALIB_MODE_MASK 0x3
67 65
68#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 66#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
69#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 67#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4