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authorAlex Deucher <alexander.deucher@amd.com>2012-03-20 17:18:13 -0400
committerDave Airlie <airlied@redhat.com>2012-03-21 02:55:52 -0400
commitd2800ee59ed28a5eaf3a4a8645feca040eacf7df (patch)
treee3418e8704703b1d65ff2528905ba3613436930a
parentc476dde2eda8c3e1af676fe3702b9fce98904cfb (diff)
drm/radeon/kms: add support for MC/VM setup on SI
Sets up the VM and adds support for the new VM ioctls. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/si.c328
-rw-r--r--drivers/gpu/drm/radeon/sid.h219
2 files changed, 547 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 58ad9008cf05..ad91c5fbb61b 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1608,3 +1608,331 @@ int si_asic_reset(struct radeon_device *rdev)
1608 return si_gpu_soft_reset(rdev); 1608 return si_gpu_soft_reset(rdev);
1609} 1609}
1610 1610
1611/* MC */
1612static void si_mc_program(struct radeon_device *rdev)
1613{
1614 struct evergreen_mc_save save;
1615 u32 tmp;
1616 int i, j;
1617
1618 /* Initialize HDP */
1619 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1620 WREG32((0x2c14 + j), 0x00000000);
1621 WREG32((0x2c18 + j), 0x00000000);
1622 WREG32((0x2c1c + j), 0x00000000);
1623 WREG32((0x2c20 + j), 0x00000000);
1624 WREG32((0x2c24 + j), 0x00000000);
1625 }
1626 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1627
1628 evergreen_mc_stop(rdev, &save);
1629 if (radeon_mc_wait_for_idle(rdev)) {
1630 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1631 }
1632 /* Lockout access through VGA aperture*/
1633 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1634 /* Update configuration */
1635 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1636 rdev->mc.vram_start >> 12);
1637 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1638 rdev->mc.vram_end >> 12);
1639 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
1640 rdev->vram_scratch.gpu_addr >> 12);
1641 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1642 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1643 WREG32(MC_VM_FB_LOCATION, tmp);
1644 /* XXX double check these! */
1645 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1646 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1647 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1648 WREG32(MC_VM_AGP_BASE, 0);
1649 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1650 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1651 if (radeon_mc_wait_for_idle(rdev)) {
1652 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1653 }
1654 evergreen_mc_resume(rdev, &save);
1655 /* we need to own VRAM, so turn off the VGA renderer here
1656 * to stop it overwriting our objects */
1657 rv515_vga_render_disable(rdev);
1658}
1659
1660/* SI MC address space is 40 bits */
1661static void si_vram_location(struct radeon_device *rdev,
1662 struct radeon_mc *mc, u64 base)
1663{
1664 mc->vram_start = base;
1665 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
1666 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
1667 mc->real_vram_size = mc->aper_size;
1668 mc->mc_vram_size = mc->aper_size;
1669 }
1670 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1671 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
1672 mc->mc_vram_size >> 20, mc->vram_start,
1673 mc->vram_end, mc->real_vram_size >> 20);
1674}
1675
1676static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1677{
1678 u64 size_af, size_bf;
1679
1680 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
1681 size_bf = mc->vram_start & ~mc->gtt_base_align;
1682 if (size_bf > size_af) {
1683 if (mc->gtt_size > size_bf) {
1684 dev_warn(rdev->dev, "limiting GTT\n");
1685 mc->gtt_size = size_bf;
1686 }
1687 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
1688 } else {
1689 if (mc->gtt_size > size_af) {
1690 dev_warn(rdev->dev, "limiting GTT\n");
1691 mc->gtt_size = size_af;
1692 }
1693 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
1694 }
1695 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
1696 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
1697 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
1698}
1699
1700static void si_vram_gtt_location(struct radeon_device *rdev,
1701 struct radeon_mc *mc)
1702{
1703 if (mc->mc_vram_size > 0xFFC0000000ULL) {
1704 /* leave room for at least 1024M GTT */
1705 dev_warn(rdev->dev, "limiting VRAM\n");
1706 mc->real_vram_size = 0xFFC0000000ULL;
1707 mc->mc_vram_size = 0xFFC0000000ULL;
1708 }
1709 si_vram_location(rdev, &rdev->mc, 0);
1710 rdev->mc.gtt_base_align = 0;
1711 si_gtt_location(rdev, mc);
1712}
1713
1714static int si_mc_init(struct radeon_device *rdev)
1715{
1716 u32 tmp;
1717 int chansize, numchan;
1718
1719 /* Get VRAM informations */
1720 rdev->mc.vram_is_ddr = true;
1721 tmp = RREG32(MC_ARB_RAMCFG);
1722 if (tmp & CHANSIZE_OVERRIDE) {
1723 chansize = 16;
1724 } else if (tmp & CHANSIZE_MASK) {
1725 chansize = 64;
1726 } else {
1727 chansize = 32;
1728 }
1729 tmp = RREG32(MC_SHARED_CHMAP);
1730 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1731 case 0:
1732 default:
1733 numchan = 1;
1734 break;
1735 case 1:
1736 numchan = 2;
1737 break;
1738 case 2:
1739 numchan = 4;
1740 break;
1741 case 3:
1742 numchan = 8;
1743 break;
1744 case 4:
1745 numchan = 3;
1746 break;
1747 case 5:
1748 numchan = 6;
1749 break;
1750 case 6:
1751 numchan = 10;
1752 break;
1753 case 7:
1754 numchan = 12;
1755 break;
1756 case 8:
1757 numchan = 16;
1758 break;
1759 }
1760 rdev->mc.vram_width = numchan * chansize;
1761 /* Could aper size report 0 ? */
1762 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1763 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1764 /* size in MB on si */
1765 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1766 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1767 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1768 si_vram_gtt_location(rdev, &rdev->mc);
1769 radeon_update_bandwidth_info(rdev);
1770
1771 return 0;
1772}
1773
1774/*
1775 * GART
1776 */
1777void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
1778{
1779 /* flush hdp cache */
1780 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1781
1782 /* bits 0-15 are the VM contexts0-15 */
1783 WREG32(VM_INVALIDATE_REQUEST, 1);
1784}
1785
1786int si_pcie_gart_enable(struct radeon_device *rdev)
1787{
1788 int r, i;
1789
1790 if (rdev->gart.robj == NULL) {
1791 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1792 return -EINVAL;
1793 }
1794 r = radeon_gart_table_vram_pin(rdev);
1795 if (r)
1796 return r;
1797 radeon_gart_restore(rdev);
1798 /* Setup TLB control */
1799 WREG32(MC_VM_MX_L1_TLB_CNTL,
1800 (0xA << 7) |
1801 ENABLE_L1_TLB |
1802 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1803 ENABLE_ADVANCED_DRIVER_MODEL |
1804 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1805 /* Setup L2 cache */
1806 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1807 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1808 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1809 EFFECTIVE_L2_QUEUE_SIZE(7) |
1810 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1811 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1812 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1813 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
1814 /* setup context0 */
1815 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1816 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1817 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1818 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1819 (u32)(rdev->dummy_page.addr >> 12));
1820 WREG32(VM_CONTEXT0_CNTL2, 0);
1821 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1822 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
1823
1824 WREG32(0x15D4, 0);
1825 WREG32(0x15D8, 0);
1826 WREG32(0x15DC, 0);
1827
1828 /* empty context1-15 */
1829 /* FIXME start with 1G, once using 2 level pt switch to full
1830 * vm size space
1831 */
1832 /* set vm size, must be a multiple of 4 */
1833 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
1834 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, (1 << 30) / RADEON_GPU_PAGE_SIZE);
1835 for (i = 1; i < 16; i++) {
1836 if (i < 8)
1837 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1838 rdev->gart.table_addr >> 12);
1839 else
1840 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
1841 rdev->gart.table_addr >> 12);
1842 }
1843
1844 /* enable context1-15 */
1845 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1846 (u32)(rdev->dummy_page.addr >> 12));
1847 WREG32(VM_CONTEXT1_CNTL2, 0);
1848 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1849 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1850
1851 si_pcie_gart_tlb_flush(rdev);
1852 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1853 (unsigned)(rdev->mc.gtt_size >> 20),
1854 (unsigned long long)rdev->gart.table_addr);
1855 rdev->gart.ready = true;
1856 return 0;
1857}
1858
1859void si_pcie_gart_disable(struct radeon_device *rdev)
1860{
1861 /* Disable all tables */
1862 WREG32(VM_CONTEXT0_CNTL, 0);
1863 WREG32(VM_CONTEXT1_CNTL, 0);
1864 /* Setup TLB control */
1865 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1866 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1867 /* Setup L2 cache */
1868 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1869 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1870 EFFECTIVE_L2_QUEUE_SIZE(7) |
1871 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1872 WREG32(VM_L2_CNTL2, 0);
1873 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1874 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
1875 radeon_gart_table_vram_unpin(rdev);
1876}
1877
1878void si_pcie_gart_fini(struct radeon_device *rdev)
1879{
1880 si_pcie_gart_disable(rdev);
1881 radeon_gart_table_vram_free(rdev);
1882 radeon_gart_fini(rdev);
1883}
1884
1885/*
1886 * vm
1887 */
1888int si_vm_init(struct radeon_device *rdev)
1889{
1890 /* number of VMs */
1891 rdev->vm_manager.nvm = 16;
1892 /* base offset of vram pages */
1893 rdev->vm_manager.vram_base_offset = 0;
1894
1895 return 0;
1896}
1897
1898void si_vm_fini(struct radeon_device *rdev)
1899{
1900}
1901
1902int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1903{
1904 if (id < 8)
1905 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1906 else
1907 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2),
1908 vm->pt_gpu_addr >> 12);
1909 /* flush hdp cache */
1910 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1911 /* bits 0-15 are the VM contexts0-15 */
1912 WREG32(VM_INVALIDATE_REQUEST, 1 << id);
1913 return 0;
1914}
1915
1916void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
1917{
1918 if (vm->id < 8)
1919 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
1920 else
1921 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0);
1922 /* flush hdp cache */
1923 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1924 /* bits 0-15 are the VM contexts0-15 */
1925 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1926}
1927
1928void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
1929{
1930 if (vm->id == -1)
1931 return;
1932
1933 /* flush hdp cache */
1934 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1935 /* bits 0-15 are the VM contexts0-15 */
1936 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1937}
1938
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 4c6ff1c8b5ed..4d9cdc813d81 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -50,6 +50,9 @@
50#define SI_MAX_TCC 16 50#define SI_MAX_TCC 16
51#define SI_MAX_TCC_MASK 0xFFFF 51#define SI_MAX_TCC_MASK 0xFFFF
52 52
53#define VGA_HDP_CONTROL 0x328
54#define VGA_MEMORY_DISABLE (1 << 4)
55
53#define DMIF_ADDR_CONFIG 0xBD4 56#define DMIF_ADDR_CONFIG 0xBD4
54 57
55#define SRBM_STATUS 0xE50 58#define SRBM_STATUS 0xE50
@@ -57,11 +60,88 @@
57#define CC_SYS_RB_BACKEND_DISABLE 0xe80 60#define CC_SYS_RB_BACKEND_DISABLE 0xe80
58#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 61#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
59 62
63#define VM_L2_CNTL 0x1400
64#define ENABLE_L2_CACHE (1 << 0)
65#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
66#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
67#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
68#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
69#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
70#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
71#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
72#define VM_L2_CNTL2 0x1404
73#define INVALIDATE_ALL_L1_TLBS (1 << 0)
74#define INVALIDATE_L2_CACHE (1 << 1)
75#define INVALIDATE_CACHE_MODE(x) ((x) << 26)
76#define INVALIDATE_PTE_AND_PDE_CACHES 0
77#define INVALIDATE_ONLY_PTE_CACHES 1
78#define INVALIDATE_ONLY_PDE_CACHES 2
79#define VM_L2_CNTL3 0x1408
80#define BANK_SELECT(x) ((x) << 0)
81#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
82#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
83#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
84#define VM_L2_STATUS 0x140C
85#define L2_BUSY (1 << 0)
86#define VM_CONTEXT0_CNTL 0x1410
87#define ENABLE_CONTEXT (1 << 0)
88#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
89#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
90#define VM_CONTEXT1_CNTL 0x1414
91#define VM_CONTEXT0_CNTL2 0x1430
92#define VM_CONTEXT1_CNTL2 0x1434
93#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
94#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
95#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
96#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
97#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
98#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
99#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
100#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
101
102#define VM_INVALIDATE_REQUEST 0x1478
103#define VM_INVALIDATE_RESPONSE 0x147c
104
105#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
106#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
107
108#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
109#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
110#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
111#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
112#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
113#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
114#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
115#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
116#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
117#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
118
119#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
120#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
121
60#define MC_SHARED_CHMAP 0x2004 122#define MC_SHARED_CHMAP 0x2004
61#define NOOFCHAN_SHIFT 12 123#define NOOFCHAN_SHIFT 12
62#define NOOFCHAN_MASK 0x0000f000 124#define NOOFCHAN_MASK 0x0000f000
63#define MC_SHARED_CHREMAP 0x2008 125#define MC_SHARED_CHREMAP 0x2008
64 126
127#define MC_VM_FB_LOCATION 0x2024
128#define MC_VM_AGP_TOP 0x2028
129#define MC_VM_AGP_BOT 0x202C
130#define MC_VM_AGP_BASE 0x2030
131#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
132#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
133#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
134
135#define MC_VM_MX_L1_TLB_CNTL 0x2064
136#define ENABLE_L1_TLB (1 << 0)
137#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
138#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
139#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
140#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
141#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
142#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
143#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
144
65#define MC_ARB_RAMCFG 0x2760 145#define MC_ARB_RAMCFG 0x2760
66#define NOOFBANK_SHIFT 0 146#define NOOFBANK_SHIFT 0
67#define NOOFBANK_MASK 0x00000003 147#define NOOFBANK_MASK 0x00000003
@@ -73,19 +153,29 @@
73#define NOOFCOLS_MASK 0x000000C0 153#define NOOFCOLS_MASK 0x000000C0
74#define CHANSIZE_SHIFT 8 154#define CHANSIZE_SHIFT 8
75#define CHANSIZE_MASK 0x00000100 155#define CHANSIZE_MASK 0x00000100
156#define CHANSIZE_OVERRIDE (1 << 11)
76#define NOOFGROUPS_SHIFT 12 157#define NOOFGROUPS_SHIFT 12
77#define NOOFGROUPS_MASK 0x00001000 158#define NOOFGROUPS_MASK 0x00001000
78 159
79#define HDP_HOST_PATH_CNTL 0x2C00 160#define HDP_HOST_PATH_CNTL 0x2C00
161#define HDP_NONSURFACE_BASE 0x2C04
162#define HDP_NONSURFACE_INFO 0x2C08
163#define HDP_NONSURFACE_SIZE 0x2C0C
80 164
81#define HDP_ADDR_CONFIG 0x2F48 165#define HDP_ADDR_CONFIG 0x2F48
82#define HDP_MISC_CNTL 0x2F4C 166#define HDP_MISC_CNTL 0x2F4C
83#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 167#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
84 168
169#define CONFIG_MEMSIZE 0x5428
170
171#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
172
85#define BIF_FB_EN 0x5490 173#define BIF_FB_EN 0x5490
86#define FB_READ_EN (1 << 0) 174#define FB_READ_EN (1 << 0)
87#define FB_WRITE_EN (1 << 1) 175#define FB_WRITE_EN (1 << 1)
88 176
177#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
178
89#define DC_LB_MEMORY_SPLIT 0x6b0c 179#define DC_LB_MEMORY_SPLIT 0x6b0c
90#define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 180#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
91 181
@@ -321,5 +411,134 @@
321#define TCP_CHAN_STEER_LO 0xac0c 411#define TCP_CHAN_STEER_LO 0xac0c
322#define TCP_CHAN_STEER_HI 0xac10 412#define TCP_CHAN_STEER_HI 0xac10
323 413
414/*
415 * PM4
416 */
417#define PACKET_TYPE0 0
418#define PACKET_TYPE1 1
419#define PACKET_TYPE2 2
420#define PACKET_TYPE3 3
421
422#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
423#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
424#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
425#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
426#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
427 (((reg) >> 2) & 0xFFFF) | \
428 ((n) & 0x3FFF) << 16)
429#define CP_PACKET2 0x80000000
430#define PACKET2_PAD_SHIFT 0
431#define PACKET2_PAD_MASK (0x3fffffff << 0)
432
433#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
434
435#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
436 (((op) & 0xFF) << 8) | \
437 ((n) & 0x3FFF) << 16)
438
439/* Packet 3 types */
440#define PACKET3_NOP 0x10
441#define PACKET3_SET_BASE 0x11
442#define PACKET3_BASE_INDEX(x) ((x) << 0)
443#define GDS_PARTITION_BASE 2
444#define CE_PARTITION_BASE 3
445#define PACKET3_CLEAR_STATE 0x12
446#define PACKET3_INDEX_BUFFER_SIZE 0x13
447#define PACKET3_DISPATCH_DIRECT 0x15
448#define PACKET3_DISPATCH_INDIRECT 0x16
449#define PACKET3_ALLOC_GDS 0x1B
450#define PACKET3_WRITE_GDS_RAM 0x1C
451#define PACKET3_ATOMIC_GDS 0x1D
452#define PACKET3_ATOMIC 0x1E
453#define PACKET3_OCCLUSION_QUERY 0x1F
454#define PACKET3_SET_PREDICATION 0x20
455#define PACKET3_REG_RMW 0x21
456#define PACKET3_COND_EXEC 0x22
457#define PACKET3_PRED_EXEC 0x23
458#define PACKET3_DRAW_INDIRECT 0x24
459#define PACKET3_DRAW_INDEX_INDIRECT 0x25
460#define PACKET3_INDEX_BASE 0x26
461#define PACKET3_DRAW_INDEX_2 0x27
462#define PACKET3_CONTEXT_CONTROL 0x28
463#define PACKET3_INDEX_TYPE 0x2A
464#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
465#define PACKET3_DRAW_INDEX_AUTO 0x2D
466#define PACKET3_DRAW_INDEX_IMMD 0x2E
467#define PACKET3_NUM_INSTANCES 0x2F
468#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
469#define PACKET3_INDIRECT_BUFFER_CONST 0x31
470#define PACKET3_INDIRECT_BUFFER 0x32
471#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
472#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
473#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
474#define PACKET3_WRITE_DATA 0x37
475#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
476#define PACKET3_MEM_SEMAPHORE 0x39
477#define PACKET3_MPEG_INDEX 0x3A
478#define PACKET3_COPY_DW 0x3B
479#define PACKET3_WAIT_REG_MEM 0x3C
480#define PACKET3_MEM_WRITE 0x3D
481#define PACKET3_COPY_DATA 0x40
482#define PACKET3_PFP_SYNC_ME 0x42
483#define PACKET3_SURFACE_SYNC 0x43
484# define PACKET3_DEST_BASE_0_ENA (1 << 0)
485# define PACKET3_DEST_BASE_1_ENA (1 << 1)
486# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
487# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
488# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
489# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
490# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
491# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
492# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
493# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
494# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
495# define PACKET3_DEST_BASE_2_ENA (1 << 19)
496# define PACKET3_DEST_BASE_3_ENA (1 << 21)
497# define PACKET3_TCL1_ACTION_ENA (1 << 22)
498# define PACKET3_TC_ACTION_ENA (1 << 23)
499# define PACKET3_CB_ACTION_ENA (1 << 25)
500# define PACKET3_DB_ACTION_ENA (1 << 26)
501# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
502# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
503#define PACKET3_ME_INITIALIZE 0x44
504#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
505#define PACKET3_COND_WRITE 0x45
506#define PACKET3_EVENT_WRITE 0x46
507#define PACKET3_EVENT_WRITE_EOP 0x47
508#define PACKET3_EVENT_WRITE_EOS 0x48
509#define PACKET3_PREAMBLE_CNTL 0x4A
510# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
511# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
512#define PACKET3_ONE_REG_WRITE 0x57
513#define PACKET3_LOAD_CONFIG_REG 0x5F
514#define PACKET3_LOAD_CONTEXT_REG 0x60
515#define PACKET3_LOAD_SH_REG 0x61
516#define PACKET3_SET_CONFIG_REG 0x68
517#define PACKET3_SET_CONFIG_REG_START 0x00008000
518#define PACKET3_SET_CONFIG_REG_END 0x0000b000
519#define PACKET3_SET_CONTEXT_REG 0x69
520#define PACKET3_SET_CONTEXT_REG_START 0x00028000
521#define PACKET3_SET_CONTEXT_REG_END 0x00029000
522#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
523#define PACKET3_SET_RESOURCE_INDIRECT 0x74
524#define PACKET3_SET_SH_REG 0x76
525#define PACKET3_SET_SH_REG_START 0x0000b000
526#define PACKET3_SET_SH_REG_END 0x0000c000
527#define PACKET3_SET_SH_REG_OFFSET 0x77
528#define PACKET3_ME_WRITE 0x7A
529#define PACKET3_SCRATCH_RAM_WRITE 0x7D
530#define PACKET3_SCRATCH_RAM_READ 0x7E
531#define PACKET3_CE_WRITE 0x7F
532#define PACKET3_LOAD_CONST_RAM 0x80
533#define PACKET3_WRITE_CONST_RAM 0x81
534#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
535#define PACKET3_DUMP_CONST_RAM 0x83
536#define PACKET3_INCREMENT_CE_COUNTER 0x84
537#define PACKET3_INCREMENT_DE_COUNTER 0x85
538#define PACKET3_WAIT_ON_CE_COUNTER 0x86
539#define PACKET3_WAIT_ON_DE_COUNTER 0x87
540#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
541#define PACKET3_SET_CE_DE_COUNTERS 0x89
542#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
324 543
325#endif 544#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-11 19:40:01 -0400