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authorSrinivas Kandagatla <srinivas.kandagatla@st.com>2014-01-29 11:20:12 -0500
committerSrinivas Kandagatla <srinivas.kandagatla@st.com>2014-03-11 06:04:13 -0400
commitd25ea5845360bfcc2771ed876887d5895ebb9d74 (patch)
tree54df0ea7dd3835408a16a767d02cbca1943ff315
parentc80fe3357fc13a4b5ecbb89a07d53c60f9df4b0a (diff)
ARM: STi: STiH416: Add ethernet support.
This patch adds support to STiH416 SOC, which has two ethernet snps,dwmac controllers version 3.710. With this patch B2000 and B2020 boards can boot with ethernet in MII and RGMII modes. Tested on both B2020 and B2000. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/stih416-clock.dtsi14
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi109
-rw-r--r--arch/arm/boot/dts/stih416.dtsi44
3 files changed, 167 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1158d8..a6942c75cbbb 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
37 clock-frequency = <100000000>; 37 clock-frequency = <100000000>;
38 clock-output-names = "CLK_S_ICN_REG_0"; 38 clock-output-names = "CLK_S_ICN_REG_0";
39 }; 39 };
40
41 CLK_S_GMAC0_PHY: clockgenA1@7 {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <25000000>;
45 clock-output-names = "CLK_S_GMAC0_PHY";
46 };
47
48 CLK_S_ETH1_PHY: clockgenA0@7 {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <25000000>;
52 clock-output-names = "CLK_S_ETH1_PHY";
53 };
40 }; 54 };
41}; 55};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 8863c38d35b8..77b7725c1075 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -132,6 +132,58 @@
132 }; 132 };
133 }; 133 };
134 }; 134 };
135
136 gmac1 {
137 pinctrl_mii1: mii1 {
138 st,pins {
139 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
140 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
141 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
142 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
143 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
144 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
145 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
146 col = <&PIO0 7 ALT1 IN BYPASS 1000>;
147
148 mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
149 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
150 crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
151 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
152 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
153 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
154 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
155 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
156
157 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
158 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
159 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
160 phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
161 };
162 };
163 pinctrl_rgmii1: rgmii1-0 {
164 st,pins {
165 txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
166 txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
167 txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
168 txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
169 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
170 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
171
172 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
173 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
174 rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
175 rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
176 rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
177 rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
178
179 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
180 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
181 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
182
183 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
184 };
185 };
186 };
135 }; 187 };
136 188
137 pin-controller-front { 189 pin-controller-front {
@@ -322,6 +374,63 @@
322 }; 374 };
323 }; 375 };
324 }; 376 };
377
378 gmac0 {
379 pinctrl_mii0: mii0 {
380 st,pins {
381 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
382 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
383 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
384 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
385 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
386 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
387
388 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
389 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
390 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
391 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
392 mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
393 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
394
395 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
396 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
397 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
398 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
399 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
400 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
401 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
402 phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
403 };
404 };
405
406 pinctrl_gmii0: gmii0 {
407 st,pins {
408 };
409 };
410 pinctrl_rgmii0: rgmii0 {
411 st,pins {
412 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
413 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
414 txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
415 txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
416 txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
417 txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
418 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
419
420 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
421 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
422
423 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
424 rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
425 rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
426 rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
427 rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
428 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
429
430 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
431 };
432 };
433 };
325 }; 434 };
326 435
327 pin-controller-fvdp-fe { 436 pin-controller-fvdp-fe {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 788ba5be9a1b..a96055b12a99 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -156,5 +156,49 @@
156 156
157 status = "disabled"; 157 status = "disabled";
158 }; 158 };
159
160 ethernet0: dwmac@fe810000 {
161 device_type = "network";
162 compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
163 status = "disabled";
164 reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
165 reg-names = "stmmaceth", "sti-ethconf";
166
167 interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
168 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
169
170 snps,pbl = <32>;
171 snps,mixed-burst;
172
173 st,syscon = <&syscfg_rear>;
174 resets = <&softreset STIH416_ETH0_SOFTRESET>;
175 reset-names = "stmmaceth";
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_mii0>;
178 clock-names = "stmmaceth";
179 clocks = <&CLK_S_GMAC0_PHY>;
180 };
181
182 ethernet1: dwmac@fef08000 {
183 device_type = "network";
184 compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
185 status = "disabled";
186 reg = <0xfef08000 0x8000>, <0x7f0 0x4>;
187 reg-names = "stmmaceth", "sti-ethconf";
188 interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
189 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
190
191 snps,pbl = <32>;
192 snps,mixed-burst;
193
194 st,syscon = <&syscfg_sbc>;
195
196 resets = <&softreset STIH416_ETH1_SOFTRESET>;
197 reset-names = "stmmaceth";
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_mii1>;
200 clock-names = "stmmaceth";
201 clocks = <&CLK_S_ETH1_PHY>;
202 };
159 }; 203 };
160}; 204};
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-28 21:53:27 -0400