drm/i915/chv: Set soft reset override bit for data lane resets

The bits we've been setting so far only progagate the reset singal to
the data lanes. To actaully force the reset signal we need to set another
override bit.

v2: Fix mispalced ';' (Mika)

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

3 files changed, 17 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1ae55fc35e4f..5d1d287f1e38 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -661,6 +661,7 @@ enum punit_power_well {
 
 #define _VLV_PCS_DW1_CH0                0x8204
 #define _VLV_PCS_DW1_CH1                0x8404
+#define   CHV_PCS_REQ_SOFTRESET_EN      (1<<23)
 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT  (6)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7235ffb58a18..37638f8e2265 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1882,6 +1882,10 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Propagate soft reset to data lane reset */
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
@@ -2023,6 +2027,10 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Deassert soft data lane reset*/
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9ea494a2a32e..f66c7a2ebd9a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1259,6 +1259,10 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Propagate soft reset to data lane reset */
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
@@ -1281,6 +1285,10 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Deassert soft data lane reset*/
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);