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authorArnd Bergmann <arnd@arndb.de>2012-04-30 18:11:33 -0400
committerArnd Bergmann <arnd@arndb.de>2012-04-30 18:12:07 -0400
commitd1ef5bd711b6b01e6a73cf186245d19939882706 (patch)
tree14842d65a25839c31cf4e99ded0410d569f1a4aa
parent26690863e2c1fa4fee5f6137b219f4b8a1a02287 (diff)
parentcce783c608fee0716cff65926d1835a5fd097b69 (diff)
Merge tag 'at91-for-next-soc' of git://github.com/at91linux/linux-at91 into next/newsoc
ARM: at91: Add at91sam9n12 and refence booard * tag 'at91-for-next-soc' of git://github.com/at91linux/linux-at91: ARM: at91: Add DT description files for AT91SAM9N12-EK ARM: at91: Add machine files for AT91SAM9N12 SoC ARM: at91: Add machine header file for AT91SAM9N12 SoC Based on at91/dt branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi221
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts84
-rw-r--r--arch/arm/mach-at91/Kconfig8
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/Makefile.boot2
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c233
-rw-r--r--arch/arm/mach-at91/clock.c15
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9n12.h60
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h53
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h10
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-at91/setup.c6
-rw-r--r--arch/arm/mach-at91/soc.h5
13 files changed, 694 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
new file mode 100644
index 000000000000..cb84de791b5a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -0,0 +1,221 @@
1/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 serial4 = &usart3;
23 gpio0 = &pioA;
24 gpio1 = &pioB;
25 gpio2 = &pioC;
26 gpio3 = &pioD;
27 tcb0 = &tcb0;
28 tcb1 = &tcb1;
29 };
30 cpus {
31 cpu@0 {
32 compatible = "arm,arm926ejs";
33 };
34 };
35
36 memory {
37 reg = <0x20000000 0x10000000>;
38 };
39
40 ahb {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 ranges;
45
46 apb {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges;
51
52 aic: interrupt-controller@fffff000 {
53 #interrupt-cells = <2>;
54 compatible = "atmel,at91rm9200-aic";
55 interrupt-controller;
56 reg = <0xfffff000 0x200>;
57 };
58
59 ramc0: ramc@ffffe800 {
60 compatible = "atmel,at91sam9g45-ddramc";
61 reg = <0xffffe800 0x200>;
62 };
63
64 pmc: pmc@fffffc00 {
65 compatible = "atmel,at91rm9200-pmc";
66 reg = <0xfffffc00 0x100>;
67 };
68
69 rstc@fffffe00 {
70 compatible = "atmel,at91sam9g45-rstc";
71 reg = <0xfffffe00 0x10>;
72 };
73
74 pit: timer@fffffe30 {
75 compatible = "atmel,at91sam9260-pit";
76 reg = <0xfffffe30 0xf>;
77 interrupts = <1 4>;
78 };
79
80 shdwc@fffffe10 {
81 compatible = "atmel,at91sam9x5-shdwc";
82 reg = <0xfffffe10 0x10>;
83 };
84
85 tcb0: timer@f8008000 {
86 compatible = "atmel,at91sam9x5-tcb";
87 reg = <0xf8008000 0x100>;
88 interrupts = <17 4>;
89 };
90
91 tcb1: timer@f800c000 {
92 compatible = "atmel,at91sam9x5-tcb";
93 reg = <0xf800c000 0x100>;
94 interrupts = <17 4>;
95 };
96
97 dma: dma-controller@ffffec00 {
98 compatible = "atmel,at91sam9g45-dma";
99 reg = <0xffffec00 0x200>;
100 interrupts = <20 4>;
101 };
102
103 pioA: gpio@fffff400 {
104 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
105 reg = <0xfffff400 0x100>;
106 interrupts = <2 4>;
107 #gpio-cells = <2>;
108 gpio-controller;
109 interrupt-controller;
110 };
111
112 pioB: gpio@fffff600 {
113 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
114 reg = <0xfffff600 0x100>;
115 interrupts = <2 4>;
116 #gpio-cells = <2>;
117 gpio-controller;
118 interrupt-controller;
119 };
120
121 pioC: gpio@fffff800 {
122 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
123 reg = <0xfffff800 0x100>;
124 interrupts = <3 4>;
125 #gpio-cells = <2>;
126 gpio-controller;
127 interrupt-controller;
128 };
129
130 pioD: gpio@fffffa00 {
131 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
132 reg = <0xfffffa00 0x100>;
133 interrupts = <3 4>;
134 #gpio-cells = <2>;
135 gpio-controller;
136 interrupt-controller;
137 };
138
139 dbgu: serial@fffff200 {
140 compatible = "atmel,at91sam9260-usart";
141 reg = <0xfffff200 0x200>;
142 interrupts = <1 4>;
143 status = "disabled";
144 };
145
146 usart0: serial@f801c000 {
147 compatible = "atmel,at91sam9260-usart";
148 reg = <0xf801c000 0x4000>;
149 interrupts = <5 4>;
150 atmel,use-dma-rx;
151 atmel,use-dma-tx;
152 status = "disabled";
153 };
154
155 usart1: serial@f8020000 {
156 compatible = "atmel,at91sam9260-usart";
157 reg = <0xf8020000 0x4000>;
158 interrupts = <6 4>;
159 atmel,use-dma-rx;
160 atmel,use-dma-tx;
161 status = "disabled";
162 };
163
164 usart2: serial@f8024000 {
165 compatible = "atmel,at91sam9260-usart";
166 reg = <0xf8024000 0x4000>;
167 interrupts = <7 4>;
168 atmel,use-dma-rx;
169 atmel,use-dma-tx;
170 status = "disabled";
171 };
172
173 usart3: serial@f8028000 {
174 compatible = "atmel,at91sam9260-usart";
175 reg = <0xf8028000 0x4000>;
176 interrupts = <8 4>;
177 atmel,use-dma-rx;
178 atmel,use-dma-tx;
179 status = "disabled";
180 };
181 };
182
183 nand0: nand@40000000 {
184 compatible = "atmel,at91rm9200-nand";
185 #address-cells = <1>;
186 #size-cells = <1>;
187 reg = < 0x40000000 0x10000000
188 0xffffe000 0x00000600
189 0xffffe600 0x00000200
190 0x00100000 0x00100000
191 >;
192 atmel,nand-addr-offset = <21>;
193 atmel,nand-cmd-offset = <22>;
194 gpios = <&pioD 5 0
195 &pioD 4 0
196 0
197 >;
198 status = "disabled";
199 };
200
201 usb0: ohci@00500000 {
202 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
203 reg = <0x00500000 0x00100000>;
204 interrupts = <22 4>;
205 status = "disabled";
206 };
207 };
208
209 i2c@0 {
210 compatible = "i2c-gpio";
211 gpios = <&pioA 30 0 /* sda */
212 &pioA 31 0 /* scl */
213 >;
214 i2c-gpio,sda-open-drain;
215 i2c-gpio,scl-open-drain;
216 i2c-gpio,delay-us = <2>; /* ~100 kHz */
217 #address-cells = <1>;
218 #size-cells = <0>;
219 status = "disabled";
220 };
221};
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
new file mode 100644
index 000000000000..f4e43e38f3a1
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -0,0 +1,84 @@
1/*
2 * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9n12.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12-EK";
14 compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
18 };
19
20 memory {
21 reg = <0x20000000 0x10000000>;
22 };
23
24 clocks {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
28
29 main_clock: clock@0 {
30 compatible = "atmel,osc", "fixed-clock";
31 clock-frequency = <16000000>;
32 };
33 };
34
35 ahb {
36 apb {
37 dbgu: serial@fffff200 {
38 status = "okay";
39 };
40 };
41
42 nand0: nand@40000000 {
43 nand-bus-width = <8>;
44 nand-ecc-mode = "soft";
45 nand-on-flash-bbt;
46 status = "okay";
47 };
48 };
49
50 leds {
51 compatible = "gpio-leds";
52
53 d8 {
54 label = "d8";
55 gpios = <&pioB 4 1>;
56 linux,default-trigger = "mmc0";
57 };
58
59 d9 {
60 label = "d6";
61 gpios = <&pioB 5 1>;
62 linux,default-trigger = "nand-disk";
63 };
64
65 d10 {
66 label = "d7";
67 gpios = <&pioB 6 0>;
68 linux,default-trigger = "heartbeat";
69 };
70 };
71
72 gpio_keys {
73 compatible = "gpio-keys";
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 enter {
78 label = "Enter";
79 gpios = <&pioB 4 1>;
80 linux,code = <28>;
81 gpio-key,wakeup;
82 };
83 };
84};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 98a42f3472d5..19505c0a3f01 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -91,6 +91,14 @@ config SOC_AT91SAM9X5
91 This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35 91 This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
92 and AT91SAM9X35. 92 and AT91SAM9X35.
93 93
94config SOC_AT91SAM9N12
95 bool "AT91SAM9N12 family"
96 select SOC_AT91SAM9
97 select HAVE_AT91_DBGU0
98 select HAVE_FB_ATMEL
99 help
100 Select this if you are using Atmel's AT91SAM9N12 SoC.
101
94choice 102choice
95 prompt "Atmel AT91 Processor Devices for non DT boards" 103 prompt "Atmel AT91 Processor Devices for non DT boards"
96 104
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 79d0f60af0b2..3bb7a51efc9d 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o
18obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o 18obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o
19obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o 19obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o
20obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o 20obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o
21obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
21obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o 22obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
22obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o 23obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
23 24
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index c03417ddbf0c..9e84fe4f2aaa 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -30,5 +30,7 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
30dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb 30dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
31# sam9g45 31# sam9g45
32dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb 32dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
33# sam9n12
34dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
33# sam9x5 35# sam9x5
34dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb 36dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
new file mode 100644
index 000000000000..08494664ab78
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -0,0 +1,233 @@
1/*
2 * SoC specific setup code for the AT91SAM9N12
3 *
4 * Copyright (C) 2012 Atmel Corporation.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/dma-mapping.h>
11
12#include <asm/irq.h>
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15#include <mach/at91sam9n12.h>
16#include <mach/at91_pmc.h>
17#include <mach/cpu.h>
18#include <mach/board.h>
19
20#include "soc.h"
21#include "generic.h"
22#include "clock.h"
23#include "sam9_smc.h"
24
25/* --------------------------------------------------------------------
26 * Clocks
27 * -------------------------------------------------------------------- */
28
29/*
30 * The peripheral clocks.
31 */
32static struct clk pioAB_clk = {
33 .name = "pioAB_clk",
34 .pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
35 .type = CLK_TYPE_PERIPHERAL,
36};
37static struct clk pioCD_clk = {
38 .name = "pioCD_clk",
39 .pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
40 .type = CLK_TYPE_PERIPHERAL,
41};
42static struct clk usart0_clk = {
43 .name = "usart0_clk",
44 .pmc_mask = 1 << AT91SAM9N12_ID_USART0,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk usart1_clk = {
48 .name = "usart1_clk",
49 .pmc_mask = 1 << AT91SAM9N12_ID_USART1,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk usart2_clk = {
53 .name = "usart2_clk",
54 .pmc_mask = 1 << AT91SAM9N12_ID_USART2,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk usart3_clk = {
58 .name = "usart3_clk",
59 .pmc_mask = 1 << AT91SAM9N12_ID_USART3,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk twi0_clk = {
63 .name = "twi0_clk",
64 .pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk twi1_clk = {
68 .name = "twi1_clk",
69 .pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk mmc_clk = {
73 .name = "mci_clk",
74 .pmc_mask = 1 << AT91SAM9N12_ID_MCI,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk spi0_clk = {
78 .name = "spi0_clk",
79 .pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk spi1_clk = {
83 .name = "spi1_clk",
84 .pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk uart0_clk = {
88 .name = "uart0_clk",
89 .pmc_mask = 1 << AT91SAM9N12_ID_UART0,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk uart1_clk = {
93 .name = "uart1_clk",
94 .pmc_mask = 1 << AT91SAM9N12_ID_UART1,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk tcb_clk = {
98 .name = "tcb_clk",
99 .pmc_mask = 1 << AT91SAM9N12_ID_TCB,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk pwm_clk = {
103 .name = "pwm_clk",
104 .pmc_mask = 1 << AT91SAM9N12_ID_PWM,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk adc_clk = {
108 .name = "adc_clk",
109 .pmc_mask = 1 << AT91SAM9N12_ID_ADC,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk dma_clk = {
113 .name = "dma_clk",
114 .pmc_mask = 1 << AT91SAM9N12_ID_DMA,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk uhp_clk = {
118 .name = "uhp",
119 .pmc_mask = 1 << AT91SAM9N12_ID_UHP,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk udp_clk = {
123 .name = "udp_clk",
124 .pmc_mask = 1 << AT91SAM9N12_ID_UDP,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk lcdc_clk = {
128 .name = "lcdc_clk",
129 .pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk ssc_clk = {
133 .name = "ssc_clk",
134 .pmc_mask = 1 << AT91SAM9N12_ID_SSC,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137
138static struct clk *periph_clocks[] __initdata = {
139 &pioAB_clk,
140 &pioCD_clk,
141 &usart0_clk,
142 &usart1_clk,
143 &usart2_clk,
144 &usart3_clk,
145 &twi0_clk,
146 &twi1_clk,
147 &mmc_clk,
148 &spi0_clk,
149 &spi1_clk,
150 &lcdc_clk,
151 &uart0_clk,
152 &uart1_clk,
153 &tcb_clk,
154 &pwm_clk,
155 &adc_clk,
156 &dma_clk,
157 &uhp_clk,
158 &udp_clk,
159 &ssc_clk,
160};
161
162static struct clk_lookup periph_clocks_lookups[] = {
163 /* lookup table for DT entries */
164 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
165 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
166 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
167 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
168 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
169 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
170 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
171 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
172 CLKDEV_CON_ID("pioA", &pioAB_clk),
173 CLKDEV_CON_ID("pioB", &pioAB_clk),
174 CLKDEV_CON_ID("pioC", &pioCD_clk),
175 CLKDEV_CON_ID("pioD", &pioCD_clk),
176 /* additional fake clock for macb_hclk */
177 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
178 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
179};
180
181/*
182 * The two programmable clocks.
183 * You must configure pin multiplexing to bring these signals out.
184 */
185static struct clk pck0 = {
186 .name = "pck0",
187 .pmc_mask = AT91_PMC_PCK0,
188 .type = CLK_TYPE_PROGRAMMABLE,
189 .id = 0,
190};
191static struct clk pck1 = {
192 .name = "pck1",
193 .pmc_mask = AT91_PMC_PCK1,
194 .type = CLK_TYPE_PROGRAMMABLE,
195 .id = 1,
196};
197
198static void __init at91sam9n12_register_clocks(void)
199{
200 int i;
201
202 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
203 clk_register(periph_clocks[i]);
204 clk_register(&pck0);
205 clk_register(&pck1);
206
207 clkdev_add_table(periph_clocks_lookups,
208 ARRAY_SIZE(periph_clocks_lookups));
209
210}
211
212/* --------------------------------------------------------------------
213 * AT91SAM9N12 processor initialization
214 * -------------------------------------------------------------------- */
215
216static void __init at91sam9n12_map_io(void)
217{
218 at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
219}
220
221void __init at91sam9n12_initialize(void)
222{
223 at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
224
225 /* Register GPIO subsystem (using DT) */
226 at91_gpio_init(NULL, 0);
227}
228
229struct at91_init_soc __initdata at91sam9n12_soc = {
230 .map_io = at91sam9n12_map_io,
231 .register_clocks = at91sam9n12_register_clocks,
232 .init = at91sam9n12_initialize,
233};
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a0f4d7424cdc..46130dad2d06 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -57,13 +57,15 @@ void __iomem *at91_pmc_base;
57 57
58#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ 58#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
59 || cpu_is_at91sam9g45() \ 59 || cpu_is_at91sam9g45() \
60 || cpu_is_at91sam9x5()) 60 || cpu_is_at91sam9x5() \
61 || cpu_is_at91sam9n12())
61 62
62#define cpu_has_300M_plla() (cpu_is_at91sam9g10()) 63#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
63 64
64#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ 65#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
65 || cpu_is_at91sam9g45() \ 66 || cpu_is_at91sam9g45() \
66 || cpu_is_at91sam9x5())) 67 || cpu_is_at91sam9x5() \
68 || cpu_is_at91sam9n12()))
67 69
68#define cpu_has_upll() (cpu_is_at91sam9g45() \ 70#define cpu_has_upll() (cpu_is_at91sam9g45() \
69 || cpu_is_at91sam9x5()) 71 || cpu_is_at91sam9x5())
@@ -77,12 +79,15 @@ void __iomem *at91_pmc_base;
77 || cpu_is_at91sam9x5())) 79 || cpu_is_at91sam9x5()))
78 80
79#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ 81#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
80 || cpu_is_at91sam9x5()) 82 || cpu_is_at91sam9x5() \
83 || cpu_is_at91sam9n12())
81 84
82#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ 85#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
83 || cpu_is_at91sam9x5()) 86 || cpu_is_at91sam9x5() \
87 || cpu_is_at91sam9n12())
84 88
85#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5()) 89#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
90 || cpu_is_at91sam9n12())
86 91
87static LIST_HEAD(clocks); 92static LIST_HEAD(clocks);
88static DEFINE_SPINLOCK(clk_lock); 93static DEFINE_SPINLOCK(clk_lock);
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
new file mode 100644
index 000000000000..d374b87c0459
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -0,0 +1,60 @@
1/*
2 * SoC specific header file for the AT91SAM9N12
3 *
4 * Copyright (C) 2012 Atmel Corporation
5 *
6 * Common definitions, based on AT91SAM9N12 SoC datasheet
7 *
8 * Licensed under GPLv2 or later
9 */
10
11#ifndef _AT91SAM9N12_H_
12#define _AT91SAM9N12_H_
13
14/*
15 * Peripheral identifiers/interrupts.
16 */
17#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
18#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
19#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
20#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
21#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
22#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
23#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
24#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
25#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
26#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
27#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
28#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
29#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
30#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
31#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
32#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
33#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
34#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
35#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
36#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
37#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
38#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
39#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
40#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
41#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
42
43/*
44 * User Peripheral physical base addresses.
45 */
46#define AT91SAM9N12_BASE_USART0 0xf801c000
47#define AT91SAM9N12_BASE_USART1 0xf8020000
48#define AT91SAM9N12_BASE_USART2 0xf8024000
49#define AT91SAM9N12_BASE_USART3 0xf8028000
50
51/*
52 * Internal Memory.
53 */
54#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
55#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
56
57#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
58#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
59
60#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
new file mode 100644
index 000000000000..40060cd62fa9
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
@@ -0,0 +1,53 @@
1/*
2 * Matrix-centric header file for the AT91SAM9N12
3 *
4 * Copyright (C) 2012 Atmel Corporation.
5 *
6 * Only EBI related registers.
7 * Write Protect register definitions may be useful.
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#ifndef _AT91SAM9N12_MATRIX_H_
13#define _AT91SAM9N12_MATRIX_H_
14
15#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
16#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
17#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
18#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
19#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
20#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
21#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
22#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
23#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
24#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
25#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
26#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
27#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
28#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
29#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
30#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
31#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
32#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
33#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
34#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
35#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
36#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
37#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
38#define AT91_MATRIX_MP_OFF (0 << 25)
39#define AT91_MATRIX_MP_ON (1 << 25)
40
41#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
42#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
43#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
44#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
45#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
46
47#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
48#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
49#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
50#define AT91_MATRIX_WPSR_WPV (1 << 0)
51#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
52
53#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 73d2fd209ce4..b6504c19d55c 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -25,6 +25,7 @@
25#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ 25#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
26#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ 26#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
27#define ARCH_ID_AT91SAM9X5 0x819a05a0 27#define ARCH_ID_AT91SAM9X5 0x819a05a0
28#define ARCH_ID_AT91SAM9N12 0x819a07a0
28 29
29#define ARCH_ID_AT91SAM9XE128 0x329973a0 30#define ARCH_ID_AT91SAM9XE128 0x329973a0
30#define ARCH_ID_AT91SAM9XE256 0x329a93a0 31#define ARCH_ID_AT91SAM9XE256 0x329a93a0
@@ -71,6 +72,9 @@ enum at91_soc_type {
71 /* SAM9X5 */ 72 /* SAM9X5 */
72 AT91_SOC_SAM9X5, 73 AT91_SOC_SAM9X5,
73 74
75 /* SAM9N12 */
76 AT91_SOC_SAM9N12,
77
74 /* Unknown type */ 78 /* Unknown type */
75 AT91_SOC_NONE 79 AT91_SOC_NONE
76}; 80};
@@ -177,6 +181,12 @@ static inline int at91_soc_is_detected(void)
177#define cpu_is_at91sam9x25() (0) 181#define cpu_is_at91sam9x25() (0)
178#endif 182#endif
179 183
184#ifdef CONFIG_SOC_AT91SAM9N12
185#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
186#else
187#define cpu_is_at91sam9n12() (0)
188#endif
189
180/* 190/*
181 * Since this is ARM, we will never run on any AVR32 CPU. But these 191 * Since this is ARM, we will never run on any AVR32 CPU. But these
182 * definitions may reduce clutter in common drivers. 192 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 3a01f8ff7e74..24b46bd14bbe 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,6 +32,7 @@
32#include <mach/at91sam9rl.h> 32#include <mach/at91sam9rl.h>
33#include <mach/at91sam9g45.h> 33#include <mach/at91sam9g45.h>
34#include <mach/at91sam9x5.h> 34#include <mach/at91sam9x5.h>
35#include <mach/at91sam9n12.h>
35 36
36/* 37/*
37 * On all at91 except rm9200 and x40 have the System Controller starts 38 * On all at91 except rm9200 and x40 have the System Controller starts
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 97cc04dc8073..34c9c27c917e 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -142,6 +142,11 @@ static void __init soc_detect(u32 dbgu_base)
142 at91_soc_initdata.type = AT91_SOC_SAM9X5; 142 at91_soc_initdata.type = AT91_SOC_SAM9X5;
143 at91_boot_soc = at91sam9x5_soc; 143 at91_boot_soc = at91sam9x5_soc;
144 break; 144 break;
145
146 case ARCH_ID_AT91SAM9N12:
147 at91_soc_initdata.type = AT91_SOC_SAM9N12;
148 at91_boot_soc = at91sam9n12_soc;
149 break;
145 } 150 }
146 151
147 /* at91sam9g10 */ 152 /* at91sam9g10 */
@@ -209,6 +214,7 @@ static const char *soc_name[] = {
209 [AT91_SOC_SAM9G45] = "at91sam9g45", 214 [AT91_SOC_SAM9G45] = "at91sam9g45",
210 [AT91_SOC_SAM9RL] = "at91sam9rl", 215 [AT91_SOC_SAM9RL] = "at91sam9rl",
211 [AT91_SOC_SAM9X5] = "at91sam9x5", 216 [AT91_SOC_SAM9X5] = "at91sam9x5",
217 [AT91_SOC_SAM9N12] = "at91sam9n12",
212 [AT91_SOC_NONE] = "Unknown" 218 [AT91_SOC_NONE] = "Unknown"
213}; 219};
214 220
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 683dddfd8b13..a9cfeb153719 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -20,6 +20,7 @@ extern struct at91_init_soc at91sam9263_soc;
20extern struct at91_init_soc at91sam9g45_soc; 20extern struct at91_init_soc at91sam9g45_soc;
21extern struct at91_init_soc at91sam9rl_soc; 21extern struct at91_init_soc at91sam9rl_soc;
22extern struct at91_init_soc at91sam9x5_soc; 22extern struct at91_init_soc at91sam9x5_soc;
23extern struct at91_init_soc at91sam9n12_soc;
23 24
24static inline int at91_soc_is_enabled(void) 25static inline int at91_soc_is_enabled(void)
25{ 26{
@@ -53,3 +54,7 @@ static inline int at91_soc_is_enabled(void)
53#if !defined(CONFIG_SOC_AT91SAM9X5) 54#if !defined(CONFIG_SOC_AT91SAM9X5)
54#define at91sam9x5_soc at91_boot_soc 55#define at91sam9x5_soc at91_boot_soc
55#endif 56#endif
57
58#if !defined(CONFIG_SOC_AT91SAM9N12)
59#define at91sam9n12_soc at91_boot_soc
60#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 17:17:53 -0400