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authorHoria Geanta <horia.geanta@freescale.com>2012-07-03 12:16:51 -0400
committerHerbert Xu <herbert@gondor.apana.org.au>2012-07-10 23:08:29 -0400
commitd1a0eb98e7a8b7e244e31430fdb1a752243e2698 (patch)
tree511f20120f7a618d8de4e690c48ad0e8bcf916a4
parentde197533485c09598215802b0e401a688e172573 (diff)
crypto: talitos - move talitos structures to header file
This patch moves the talitos structure definitions from c file to its header file so that the same can be shared on need basis. Signed-off-by: Sandeep Malik <Sandeep.Malik@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat
-rw-r--r--drivers/crypto/talitos.c111
-rw-r--r--drivers/crypto/talitos.h111
2 files changed, 111 insertions, 111 deletions
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 921039e56f87..bb3e63f5596b 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -53,117 +53,6 @@
53 53
54#include "talitos.h" 54#include "talitos.h"
55 55
56#define TALITOS_TIMEOUT 100000
57#define TALITOS_MAX_DATA_LEN 65535
58
59#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
60#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
61#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
62
63/* descriptor pointer entry */
64struct talitos_ptr {
65 __be16 len; /* length */
66 u8 j_extent; /* jump to sg link table and/or extent */
67 u8 eptr; /* extended address */
68 __be32 ptr; /* address */
69};
70
71static const struct talitos_ptr zero_entry = {
72 .len = 0,
73 .j_extent = 0,
74 .eptr = 0,
75 .ptr = 0
76};
77
78/* descriptor */
79struct talitos_desc {
80 __be32 hdr; /* header high bits */
81 __be32 hdr_lo; /* header low bits */
82 struct talitos_ptr ptr[7]; /* ptr/len pair array */
83};
84
85/**
86 * talitos_request - descriptor submission request
87 * @desc: descriptor pointer (kernel virtual)
88 * @dma_desc: descriptor's physical bus address
89 * @callback: whom to call when descriptor processing is done
90 * @context: caller context (optional)
91 */
92struct talitos_request {
93 struct talitos_desc *desc;
94 dma_addr_t dma_desc;
95 void (*callback) (struct device *dev, struct talitos_desc *desc,
96 void *context, int error);
97 void *context;
98};
99
100/* per-channel fifo management */
101struct talitos_channel {
102 void __iomem *reg;
103
104 /* request fifo */
105 struct talitos_request *fifo;
106
107 /* number of requests pending in channel h/w fifo */
108 atomic_t submit_count ____cacheline_aligned;
109
110 /* request submission (head) lock */
111 spinlock_t head_lock ____cacheline_aligned;
112 /* index to next free descriptor request */
113 int head;
114
115 /* request release (tail) lock */
116 spinlock_t tail_lock ____cacheline_aligned;
117 /* index to next in-progress/done descriptor request */
118 int tail;
119};
120
121struct talitos_private {
122 struct device *dev;
123 struct platform_device *ofdev;
124 void __iomem *reg;
125 int irq[2];
126
127 /* SEC global registers lock */
128 spinlock_t reg_lock ____cacheline_aligned;
129
130 /* SEC version geometry (from device tree node) */
131 unsigned int num_channels;
132 unsigned int chfifo_len;
133 unsigned int exec_units;
134 unsigned int desc_types;
135
136 /* SEC Compatibility info */
137 unsigned long features;
138
139 /*
140 * length of the request fifo
141 * fifo_len is chfifo_len rounded up to next power of 2
142 * so we can use bitwise ops to wrap
143 */
144 unsigned int fifo_len;
145
146 struct talitos_channel *chan;
147
148 /* next channel to be assigned next incoming descriptor */
149 atomic_t last_chan ____cacheline_aligned;
150
151 /* request callback tasklet */
152 struct tasklet_struct done_task[2];
153
154 /* list of registered algorithms */
155 struct list_head alg_list;
156
157 /* hwrng device */
158 struct hwrng rng;
159};
160
161/* .features flag */
162#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
163#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
164#define TALITOS_FTR_SHA224_HWINIT 0x00000004
165#define TALITOS_FTR_HMAC_OK 0x00000008
166
167static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr) 56static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
168{ 57{
169 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr)); 58 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index 3c173954ef29..9835e3abd89f 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -28,6 +28,117 @@
28 * 28 *
29 */ 29 */
30 30
31#define TALITOS_TIMEOUT 100000
32#define TALITOS_MAX_DATA_LEN 65535
33
34#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
35#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
36#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
37
38/* descriptor pointer entry */
39struct talitos_ptr {
40 __be16 len; /* length */
41 u8 j_extent; /* jump to sg link table and/or extent */
42 u8 eptr; /* extended address */
43 __be32 ptr; /* address */
44};
45
46static const struct talitos_ptr zero_entry = {
47 .len = 0,
48 .j_extent = 0,
49 .eptr = 0,
50 .ptr = 0
51};
52
53/* descriptor */
54struct talitos_desc {
55 __be32 hdr; /* header high bits */
56 __be32 hdr_lo; /* header low bits */
57 struct talitos_ptr ptr[7]; /* ptr/len pair array */
58};
59
60/**
61 * talitos_request - descriptor submission request
62 * @desc: descriptor pointer (kernel virtual)
63 * @dma_desc: descriptor's physical bus address
64 * @callback: whom to call when descriptor processing is done
65 * @context: caller context (optional)
66 */
67struct talitos_request {
68 struct talitos_desc *desc;
69 dma_addr_t dma_desc;
70 void (*callback) (struct device *dev, struct talitos_desc *desc,
71 void *context, int error);
72 void *context;
73};
74
75/* per-channel fifo management */
76struct talitos_channel {
77 void __iomem *reg;
78
79 /* request fifo */
80 struct talitos_request *fifo;
81
82 /* number of requests pending in channel h/w fifo */
83 atomic_t submit_count ____cacheline_aligned;
84
85 /* request submission (head) lock */
86 spinlock_t head_lock ____cacheline_aligned;
87 /* index to next free descriptor request */
88 int head;
89
90 /* request release (tail) lock */
91 spinlock_t tail_lock ____cacheline_aligned;
92 /* index to next in-progress/done descriptor request */
93 int tail;
94};
95
96struct talitos_private {
97 struct device *dev;
98 struct platform_device *ofdev;
99 void __iomem *reg;
100 int irq[2];
101
102 /* SEC global registers lock */
103 spinlock_t reg_lock ____cacheline_aligned;
104
105 /* SEC version geometry (from device tree node) */
106 unsigned int num_channels;
107 unsigned int chfifo_len;
108 unsigned int exec_units;
109 unsigned int desc_types;
110
111 /* SEC Compatibility info */
112 unsigned long features;
113
114 /*
115 * length of the request fifo
116 * fifo_len is chfifo_len rounded up to next power of 2
117 * so we can use bitwise ops to wrap
118 */
119 unsigned int fifo_len;
120
121 struct talitos_channel *chan;
122
123 /* next channel to be assigned next incoming descriptor */
124 atomic_t last_chan ____cacheline_aligned;
125
126 /* request callback tasklet */
127 struct tasklet_struct done_task[2];
128
129 /* list of registered algorithms */
130 struct list_head alg_list;
131
132 /* hwrng device */
133 struct hwrng rng;
134};
135
136/* .features flag */
137#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
138#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
139#define TALITOS_FTR_SHA224_HWINIT 0x00000004
140#define TALITOS_FTR_HMAC_OK 0x00000008
141
31/* 142/*
32 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register 143 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
33 */ 144 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 13:20:58 -0400