diff options
| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2014-10-22 14:00:42 -0400 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2014-10-22 21:59:07 -0400 |
| commit | d11ac1d2d556ca8495e06d7c00fe5a96e4934e98 (patch) | |
| tree | 77f6c22268c7ced51c6d72fd8626c4d683f0319d | |
| parent | 3a4356c0c042a5f340c8d6ee1a4feaa1c8e51ea2 (diff) | |
ARM: dts: socfpga: rename gpio nodes
Since the Synopsys GPIO IP can support multiple ports of varying widths, it
would make more sense to have the GPIO node DTS entry as this:
gpio0: gpio@ff708000{
porta{
};
};
Also, this is documented in the snps-dwapb-gpio.txt.
Suggested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 45fce2cf6fed..4472fd92685c 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
| @@ -547,7 +547,7 @@ | |||
| 547 | status = "disabled"; | 547 | status = "disabled"; |
| 548 | }; | 548 | }; |
| 549 | 549 | ||
| 550 | gpio@ff708000 { | 550 | gpio0: gpio@ff708000 { |
| 551 | #address-cells = <1>; | 551 | #address-cells = <1>; |
| 552 | #size-cells = <0>; | 552 | #size-cells = <0>; |
| 553 | compatible = "snps,dw-apb-gpio"; | 553 | compatible = "snps,dw-apb-gpio"; |
| @@ -555,7 +555,7 @@ | |||
| 555 | clocks = <&per_base_clk>; | 555 | clocks = <&per_base_clk>; |
| 556 | status = "disabled"; | 556 | status = "disabled"; |
| 557 | 557 | ||
| 558 | gpio0: gpio-controller@0 { | 558 | porta: gpio-controller@0 { |
| 559 | compatible = "snps,dw-apb-gpio-port"; | 559 | compatible = "snps,dw-apb-gpio-port"; |
| 560 | gpio-controller; | 560 | gpio-controller; |
| 561 | #gpio-cells = <2>; | 561 | #gpio-cells = <2>; |
| @@ -567,7 +567,7 @@ | |||
| 567 | }; | 567 | }; |
| 568 | }; | 568 | }; |
| 569 | 569 | ||
| 570 | gpio@ff709000 { | 570 | gpio1: gpio@ff709000 { |
| 571 | #address-cells = <1>; | 571 | #address-cells = <1>; |
| 572 | #size-cells = <0>; | 572 | #size-cells = <0>; |
| 573 | compatible = "snps,dw-apb-gpio"; | 573 | compatible = "snps,dw-apb-gpio"; |
| @@ -575,7 +575,7 @@ | |||
| 575 | clocks = <&per_base_clk>; | 575 | clocks = <&per_base_clk>; |
| 576 | status = "disabled"; | 576 | status = "disabled"; |
| 577 | 577 | ||
| 578 | gpio1: gpio-controller@0 { | 578 | portb: gpio-controller@0 { |
| 579 | compatible = "snps,dw-apb-gpio-port"; | 579 | compatible = "snps,dw-apb-gpio-port"; |
| 580 | gpio-controller; | 580 | gpio-controller; |
| 581 | #gpio-cells = <2>; | 581 | #gpio-cells = <2>; |
| @@ -587,7 +587,7 @@ | |||
| 587 | }; | 587 | }; |
| 588 | }; | 588 | }; |
| 589 | 589 | ||
| 590 | gpio@ff70a000 { | 590 | gpio2: gpio@ff70a000 { |
| 591 | #address-cells = <1>; | 591 | #address-cells = <1>; |
| 592 | #size-cells = <0>; | 592 | #size-cells = <0>; |
| 593 | compatible = "snps,dw-apb-gpio"; | 593 | compatible = "snps,dw-apb-gpio"; |
| @@ -595,7 +595,7 @@ | |||
| 595 | clocks = <&per_base_clk>; | 595 | clocks = <&per_base_clk>; |
| 596 | status = "disabled"; | 596 | status = "disabled"; |
| 597 | 597 | ||
| 598 | gpio2: gpio-controller@0 { | 598 | portc: gpio-controller@0 { |
| 599 | compatible = "snps,dw-apb-gpio-port"; | 599 | compatible = "snps,dw-apb-gpio-port"; |
| 600 | gpio-controller; | 600 | gpio-controller; |
| 601 | #gpio-cells = <2>; | 601 | #gpio-cells = <2>; |
