Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6

* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
  [IA64] ioremap() should prefer WB over UC
  [IA64] Add __mca_table to the DISCARD list in gate.lds
  [IA64] Move __mca_table out of the __init section
  [IA64] simplify some condition checks in iosapic_check_gsi_range
  [IA64] correct some messages and fixes some minor things
  [IA64-SGI] fix for-loop in sn_hwperf_geoid_to_cnode()
  [IA64-SGI] sn_hwperf use of num_online_cpus()
  [IA64] optimize flush_tlb_range on large numa box
  [IA64] lazy_mmu_prot_update needs to be aware of huge pages

8 files changed, 199 insertions, 123 deletions

diff --git a/arch/ia64/kernel/gate.lds.S b/arch/ia64/kernel/gate.lds.S
index e1e4aba9ecd0..7c99e6ec3daf 100644
--- a/arch/ia64/kernel/gate.lds.S
+++ b/arch/ia64/kernel/gate.lds.S
@@ -59,6 +59,7 @@ SECTIONS
         *(.dynbss)
         *(.bss .bss.* .gnu.linkonce.b.*)
         *(__ex_table)
+        *(__mca_table)
   }
 }
 
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index 8832c553230a..7956eb9058fc 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -9,54 +9,65 @@
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  *
- * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O APIC code.
- *                              In particular, we now have separate handlers for edge
- *                              and level triggered interrupts.
- * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
- *                              PCI to vector mapping, shared PCI interrupts.
- * 00/10/27     D. Mosberger    Document things a bit more to make them more understandable.
- *                              Clean up much of the old IOSAPIC cruft.
- * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts and fixes for
- *                              ACPI S5(SoftOff) support.
+ * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
+ *                              APIC code.  In particular, we now have separate
+ *                              handlers for edge and level triggered
+ *                              interrupts.
+ * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
+ *                              allocation PCI to vector mapping, shared PCI
+ *                              interrupts.
+ * 00/10/27     D. Mosberger    Document things a bit more to make them more
+ *                              understandable.  Clean up much of the old
+ *                              IOSAPIC cruft.
+ * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
+ *                              and fixes for ACPI S5(SoftOff) support.
  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
- * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt vectors in
- *                              iosapic_set_affinity(), initializations for
- *                              /proc/irq/#/smp_affinity
+ * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
+ *                              vectors in iosapic_set_affinity(),
+ *                              initializations for /proc/irq/#/smp_affinity
  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
- * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
- *                              error
+ * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
+ *                              IOSAPIC mapping error
  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
- * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system interrupt, vector, etc.)
- * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's pci_irq code.
+ * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
+ *                              interrupt, vector, etc.)
+ * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
+ *                              pci_irq code.
  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
- *                              Remove iosapic_address & gsi_base from external interfaces.
- *                              Rationalize __init/__devinit attributes.
+ *                              Remove iosapic_address & gsi_base from
+ *                              external interfaces.  Rationalize
+ *                              __init/__devinit attributes.
  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
- *                              Updated to work with irq migration necessary for CPU Hotplug
+ *                              Updated to work with irq migration necessary
+ *                              for CPU Hotplug
  */
 /*
- * Here is what the interrupt logic between a PCI device and the kernel looks like:
+ * Here is what the interrupt logic between a PCI device and the kernel looks
+ * like:
  *
- * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD).  The
- *     device is uniquely identified by its bus--, and slot-number (the function
- *     number does not matter here because all functions share the same interrupt
- *     lines).
+ * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
+ *     INTD).  The device is uniquely identified by its bus-, and slot-number
+ *     (the function number does not matter here because all functions share
+ *     the same interrupt lines).
  *
- * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
- *     Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
- *     triggered and use the same polarity).  Each interrupt line has a unique Global
- *     System Interrupt (GSI) number which can be calculated as the sum of the controller's
- *     base GSI number and the IOSAPIC pin number to which the line connects.
+ * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
+ *     controller.  Multiple interrupt lines may have to share the same
+ *     IOSAPIC pin (if they're level triggered and use the same polarity).
+ *     Each interrupt line has a unique Global System Interrupt (GSI) number
+ *     which can be calculated as the sum of the controller's base GSI number
+ *     and the IOSAPIC pin number to which the line connects.
  *
- * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
- *     into the IA-64 interrupt vector.  This interrupt vector is then sent to the CPU.
+ * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
+ * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
+ * sent to the CPU.
  *
- * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is used as
- *     architecture-independent interrupt handling mechanism in Linux.  As an
- *     IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
- *     mapping.  On smaller systems, we use one-to-one mapping between IA-64 vector and
- *     IRQ.  A platform can implement platform_irq_to_vector(irq) and
+ * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
+ *     used as architecture-independent interrupt handling mechanism in Linux.
+ *     As an IRQ is a number, we have to have
+ *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
+ *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
+ *     platform can implement platform_irq_to_vector(irq) and
  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  *     Please see also include/asm-ia64/hw_irq.h for those APIs.
  *
@@ -64,9 +75,9 @@
  *
  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  *
- * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
- * Now we use "IRQ" only for Linux IRQ's.  ISA IRQ (isa_irq) is the only exception in this
- * source code.
+ * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
+ * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
+ * (isa_irq) is the only exception in this source code.
  */
 #include <linux/config.h>
 
@@ -90,7 +101,6 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
-
 #undef DEBUG_INTERRUPT_ROUTING
 
 #ifdef DEBUG_INTERRUPT_ROUTING
@@ -99,36 +109,46 @@
 #define DBG(fmt...)
 #endif
 
-#define NR_PREALLOCATE_RTE_ENTRIES      (PAGE_SIZE / sizeof(struct iosapic_rte_info))
+#define NR_PREALLOCATE_RTE_ENTRIES \
+        (PAGE_SIZE / sizeof(struct iosapic_rte_info))
 #define RTE_PREALLOCATED        (1)
 
 static DEFINE_SPINLOCK(iosapic_lock);
 
-/* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
+/*
+ * These tables map IA-64 vectors to the IOSAPIC pin that generates this
+ * vector.
+ */
 
 struct iosapic_rte_info {
-        struct list_head rte_list;      /* node in list of RTEs sharing the same vector */
+        struct list_head rte_list;      /* node in list of RTEs sharing the
+                                         * same vector */
         char __iomem    *addr;          /* base address of IOSAPIC */
-        unsigned int    gsi_base;       /* first GSI assigned to this IOSAPIC */
+        unsigned int    gsi_base;       /* first GSI assigned to this
+                                         * IOSAPIC */
         char            rte_index;      /* IOSAPIC RTE index */
         int             refcnt;         /* reference counter */
         unsigned int    flags;          /* flags */