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authorAlex Deucher <alexdeucher@gmail.com>2010-07-27 11:17:44 -0400
committerDave Airlie <airlied@redhat.com>2010-08-01 20:07:24 -0400
commitd0623a3e74610aff0b984d68bbc027a7e511e686 (patch)
tree7c8a6e4ea59ed6ec4a6bcca1243d6a2bcff23309
parent363c6a16e30464fddcb8f82b7e8f44109729cc95 (diff)
drm/radeon: reorder r6xx/r7xx blit state emit to make more regs sequential
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.c368
1 files changed, 184 insertions, 184 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
index 9a0553c69f1b..9a0c947b342c 100644
--- a/drivers/gpu/drm/radeon/r600_blit_shaders.c
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
@@ -96,11 +96,6 @@ const u32 r6xx_default_state[] =
96 0x00000000, /* DB_STENCIL_CLEAR */ 96 0x00000000, /* DB_STENCIL_CLEAR */
97 0x00000000, /* DB_DEPTH_CLEAR */ 97 0x00000000, /* DB_DEPTH_CLEAR */
98 98
99 0xc0026900,
100 0x0000010c,
101 0x00000000, /* DB_STENCILREFMASK */
102 0x00000000, /* DB_STENCILREFMASK_BF */
103
104 0xc0016900, 99 0xc0016900,
105 0x00000200, 100 0x00000200,
106 0x00000000, /* DB_DEPTH_CONTROL */ 101 0x00000000, /* DB_DEPTH_CONTROL */
@@ -114,13 +109,19 @@ const u32 r6xx_default_state[] =
114 0x00000351, 109 0x00000351,
115 0x0000aa00, /* DB_ALPHA_TO_MASK */ 110 0x0000aa00, /* DB_ALPHA_TO_MASK */
116 111
112 0xc0036900,
113 0x00000100,
114 0x00000800, /* VGT_MAX_VTX_INDX */
115 0x00000000, /* VGT_MIN_VTX_INDX */
116 0x00000000, /* VGT_INDX_OFFSET */
117
117 0xc0016900, 118 0xc0016900,
118 0x00000104, 119 0x00000103,
119 0x00000000, /* SX_ALPHA_TEST_CONTROL */ 120 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
120 121
121 0xc0016900, 122 0xc0016900,
122 0x0000010e, 123 0x00000104,
123 0x00000000, /* SX_ALPHA_REF */ 124 0x00000000, /* SX_ALPHA_TEST_CONTROL */
124 125
125 0xc0076900, 126 0xc0076900,
126 0x00000105, 127 0x00000105,
@@ -132,6 +133,15 @@ const u32 r6xx_default_state[] =
132 0x00000000, 133 0x00000000,
133 0x00000000, 134 0x00000000,
134 135
136 0xc0026900,
137 0x0000010c,
138 0x00000000, /* DB_STENCILREFMASK */
139 0x00000000, /* DB_STENCILREFMASK_BF */
140
141 0xc0016900,
142 0x0000010e,
143 0x00000000, /* SX_ALPHA_REF */
144
135 0xc0046900, 145 0xc0046900,
136 0x0000030c, 146 0x0000030c,
137 0x01000000, /* CB_CLRCMP_CNTL */ 147 0x01000000, /* CB_CLRCMP_CNTL */
@@ -147,10 +157,6 @@ const u32 r6xx_default_state[] =
147 0x3f800000, 157 0x3f800000,
148 158
149 0xc0016900, 159 0xc0016900,
150 0x0000008e,
151 0x0000000f, /* CB_TARGET_MASK */
152
153 0xc0016900,
154 0x00000080, 160 0x00000080,
155 0x00000000, /* PA_SC_WINDOW_OFFSET */ 161 0x00000000, /* PA_SC_WINDOW_OFFSET */
156 162
@@ -235,31 +241,13 @@ const u32 r6xx_default_state[] =
235 0x3f800000, 241 0x3f800000,
236 242
237 0xc0016900, 243 0xc0016900,
238 0x00000293,
239 0x00004010, /* PA_SC_MODE_CNTL */
240
241 0xc0026900,
242 0x00000300,
243 0x00000000, /* PA_SC_LINE_CNTL */
244 0x00000000, /* PA_SC_AA_CONFIG */
245
246 0xc0016900,
247 0x00000312,
248 0xffffffff, /* PA_SC_AA_MASK */
249
250 0xc0026900,
251 0x00000307,
252 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
253 0x00000000,
254
255 0xc0016900,
256 0x00000283,
257 0x00000000, /* PA_SC_LINE_STIPPLE */
258
259 0xc0016900,
260 0x00000292, 244 0x00000292,
261 0x00000000, /* PA_SC_MPASS_PS_CNTL */ 245 0x00000000, /* PA_SC_MPASS_PS_CNTL */
262 246
247 0xc0016900,
248 0x00000293,
249 0x00004010, /* PA_SC_MODE_CNTL */
250
263 0xc0066900, 251 0xc0066900,
264 0x0000010f, 252 0x0000010f,
265 0x00000000, /* PA_CL_VPORT_0_XSCALE */ 253 0x00000000, /* PA_CL_VPORT_0_XSCALE */
@@ -270,9 +258,13 @@ const u32 r6xx_default_state[] =
270 0x00000000, 258 0x00000000,
271 259
272 0xc0026900, 260 0xc0026900,
273 0x00000207, 261 0x00000300,
274 0x00000000, /* PA_CL_VS_OUT_CNTL */ 262 0x00000000, /* PA_SC_LINE_CNTL */
275 0x00000000, /* PA_CL_NANINF_CNTL */ 263 0x00000000, /* PA_SC_AA_CONFIG */
264
265 0xc0016900,
266 0x00000302,
267 0x0000002d, /* PA_SU_VTX_CNTL */
276 268
277 0xc0046900, 269 0xc0046900,
278 0x00000303, 270 0x00000303,
@@ -282,45 +274,37 @@ const u32 r6xx_default_state[] =
282 0x3f800000, 274 0x3f800000,
283 275
284 0xc0026900, 276 0xc0026900,
285 0x00000280, 277 0x00000307,
286 0x00000000, /* PA_SU_POINT_SIZE */ 278 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
287 0x00000000, /* PA_SU_POINT_MINMAX */ 279 0x00000000,
280
281 0xc0016900,
282 0x00000312,
283 0xffffffff, /* PA_SC_AA_MASK */
288 284
289 0xc0016900, 285 0xc0016900,
290 0x0000037e, 286 0x0000037e,
291 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 287 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
292 288
293 0xc0016900, 289 0xc0016900,
294 0x00000382, 290 0x0000037f,
295 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ 291 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
296 292
297 0xc0016900, 293 0xc0016900,
298 0x00000380, 294 0x00000380,
299 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ 295 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
300 296
301 0xc0016900, 297 0xc0016900,
302 0x00000383,
303 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
304
305 0xc0016900,
306 0x00000381, 298 0x00000381,
307 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ 299 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
308 300
309 0xc0016900, 301 0xc0016900,
310 0x00000282, 302 0x00000382,
311 0x00000008, /* PA_SU_LINE_CNTL */ 303 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
312
313 0xc0016900,
314 0x00000302,
315 0x0000002d, /* PA_SU_VTX_CNTL */
316
317 0xc0016900,
318 0x0000037f,
319 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
320 304
321 0xc0016900, 305 0xc0016900,
322 0x000001b2, 306 0x00000383,
323 0x00000000, /* SPI_THREAD_GROUPING */ 307 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
324 308
325 0xc0046900, 309 0xc0046900,
326 0x000001b6, 310 0x000001b6,
@@ -341,28 +325,27 @@ const u32 r6xx_default_state[] =
341 0x00000237, 325 0x00000237,
342 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ 326 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
343 327
344 0xc0036900,
345 0x00000100,
346 0x00000800, /* VGT_MAX_VTX_INDX */
347 0x00000000, /* VGT_MIN_VTX_INDX */
348 0x00000000, /* VGT_INDX_OFFSET */
349
350 0xc0026900, 328 0xc0026900,
351 0x000002a8, 329 0x000002a8,
352 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 330 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
353 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ 331 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
354 332
333 0xc0026900,
334 0x00000280,
335 0x00000000, /* PA_SU_POINT_SIZE */
336 0x00000000, /* PA_SU_POINT_MINMAX */
337
355 0xc0016900, 338 0xc0016900,
356 0x00000103, 339 0x00000282,
357 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 340 0x00000008, /* PA_SU_LINE_CNTL */
358 341
359 0xc0016900, 342 0xc0016900,
360 0x00000284, 343 0x00000283,
361 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 344 0x00000000, /* PA_SC_LINE_STIPPLE */
362 345
363 0xc0016900, 346 0xc0016900,
364 0x00000290, 347 0x00000284,
365 0x00000000, /* VGT_GS_MODE */ 348 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
366 349
367 0xc0016900, 350 0xc0016900,
368 0x00000285, 351 0x00000285,
@@ -382,6 +365,10 @@ const u32 r6xx_default_state[] =
382 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ 365 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
383 366
384 0xc0016900, 367 0xc0016900,
368 0x00000290,
369 0x00000000, /* VGT_GS_MODE */
370
371 0xc0016900,
385 0x000002a1, 372 0x000002a1,
386 0x00000000, /* VGT_PRIMITIVEID_EN */ 373 0x00000000, /* VGT_PRIMITIVEID_EN */
387 374
@@ -400,18 +387,33 @@ const u32 r6xx_default_state[] =
400 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ 387 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
401 388
402 0xc0016900, 389 0xc0016900,
403 0x00000206, 390 0x00000202,
404 0x00000100, /* PA_CL_VTE_CNTL */ 391 0x00cc0000, /* CB_COLOR_CONTROL */
392
393 0xc0016900,
394 0x00000203,
395 0x00000210, /* DB_SHADER_CNTL */
405 396
406 0xc0016900, 397 0xc0016900,
407 0x00000204, 398 0x00000204,
408 0x00010000, /* PA_CL_CLIP_CNTL */ 399 0x00010000, /* PA_CL_CLIP_CNTL */
409 400
410 0xc0036e00, /* SET_SAMPLER */ 401 0xc0016900,
411 0x00000000, 402 0x00000205,
412 0x00000012, 403 0x00000244, /* PA_SU_SC_MODE_CNTL */
413 0x00000000, 404
414 0x00000000, 405 0xc0016900,
406 0x00000206,
407 0x00000100, /* PA_CL_VTE_CNTL */
408
409 0xc0026900,
410 0x00000207,
411 0x00000000, /* PA_CL_VS_OUT_CNTL */
412 0x00000000, /* PA_CL_NANINF_CNTL */
413
414 0xc0016900,
415 0x0000008e,
416 0x0000000f, /* CB_TARGET_MASK */
415 417
416 0xc0016900, 418 0xc0016900,
417 0x0000008f, 419 0x0000008f,
@@ -422,24 +424,20 @@ const u32 r6xx_default_state[] =
422 0x00000001, /* CB_SHADER_CONTROL */ 424 0x00000001, /* CB_SHADER_CONTROL */
423 425
424 0xc0016900, 426 0xc0016900,
425 0x00000202, 427 0x00000185,
426 0x00cc0000, /* CB_COLOR_CONTROL */ 428 0x00000000, /* SPI_VS_OUT_ID_0 */
427
428 0xc0016900,
429 0x00000205,
430 0x00000244, /* PA_SU_SC_MODE_CNTL */
431 429
432 0xc0016900, 430 0xc0016900,
433 0x00000203, 431 0x00000191,
434 0x00000210, /* DB_SHADER_CNTL */ 432 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
435 433
436 0xc0016900, 434 0xc0016900,
437 0x000001b1, 435 0x000001b1,
438 0x00000000, /* SPI_VS_OUT_CONFIG */ 436 0x00000000, /* SPI_VS_OUT_CONFIG */
439 437
440 0xc0016900, 438 0xc0016900,
441 0x00000185, 439 0x000001b2,
442 0x00000000, /* SPI_VS_OUT_ID_0 */ 440 0x00000000, /* SPI_THREAD_GROUPING */
443 441
444 0xc0026900, 442 0xc0026900,
445 0x000001b3, 443 0x000001b3,
@@ -447,12 +445,14 @@ const u32 r6xx_default_state[] =
447 0x00000000, /* SPI_PS_IN_CONTROL_1 */ 445 0x00000000, /* SPI_PS_IN_CONTROL_1 */
448 446
449 0xc0016900, 447 0xc0016900,
450 0x00000191,
451 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
452
453 0xc0016900,
454 0x000001b5, 448 0x000001b5,
455 0x00000000, /* SPI_INTERP_CONTROL_0 */ 449 0x00000000, /* SPI_INTERP_CONTROL_0 */
450
451 0xc0036e00, /* SET_SAMPLER */
452 0x00000000,
453 0x00000012,
454 0x00000000,
455 0x00000000,
456}; 456};
457 457
458const u32 r7xx_default_state[] = 458const u32 r7xx_default_state[] =
@@ -511,11 +511,6 @@ const u32 r7xx_default_state[] =
511 0x00000000, /* DB_STENCIL_CLEAR */ 511 0x00000000, /* DB_STENCIL_CLEAR */
512 0x00000000, /* DB_DEPTH_CLEAR */ 512 0x00000000, /* DB_DEPTH_CLEAR */
513 513
514 0xc0026900,
515 0x0000010c,
516 0x00000000, /* DB_STENCILREFMASK */
517 0x00000000, /* DB_STENCILREFMASK_BF */
518
519 0xc0016900, 514 0xc0016900,
520 0x00000200, 515 0x00000200,
521 0x00000000, /* DB_DEPTH_CONTROL */ 516 0x00000000, /* DB_DEPTH_CONTROL */
@@ -529,13 +524,19 @@ const u32 r7xx_default_state[] =
529 0x00000351, 524 0x00000351,
530 0x0000aa00, /* DB_ALPHA_TO_MASK */ 525 0x0000aa00, /* DB_ALPHA_TO_MASK */
531 526
527 0xc0036900,
528 0x00000100,
529 0x00000800, /* VGT_MAX_VTX_INDX */
530 0x00000000, /* VGT_MIN_VTX_INDX */
531 0x00000000, /* VGT_INDX_OFFSET */
532
532 0xc0016900, 533 0xc0016900,
533 0x00000104, 534 0x00000103,
534 0x00000000, /* SX_ALPHA_TEST_CONTROL */ 535 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
535 536
536 0xc0016900, 537 0xc0016900,
537 0x0000010e, 538 0x00000104,
538 0x00000000, /* SX_ALPHA_REF */ 539 0x00000000, /* SX_ALPHA_TEST_CONTROL */
539 540
540 0xc0046900, 541 0xc0046900,
541 0x00000105, 542 0x00000105,
@@ -544,6 +545,15 @@ const u32 r7xx_default_state[] =
544 0x00000000, 545 0x00000000,
545 0x00000000, 546 0x00000000,
546 547
548 0xc0026900,
549 0x0000010c,
550 0x00000000, /* DB_STENCILREFMASK */
551 0x00000000, /* DB_STENCILREFMASK_BF */
552
553 0xc0016900,
554 0x0000010e,
555 0x00000000, /* SX_ALPHA_REF */
556
547 0xc0046900, 557 0xc0046900,
548 0x0000030c, /* CB_CLRCMP_CNTL */ 558 0x0000030c, /* CB_CLRCMP_CNTL */
549 0x01000000, 559 0x01000000,
@@ -552,10 +562,6 @@ const u32 r7xx_default_state[] =
552 0x00000000, 562 0x00000000,
553 563
554 0xc0016900, 564 0xc0016900,
555 0x0000008e,
556 0x0000000f, /* CB_TARGET_MASK */
557
558 0xc0016900,
559 0x00000080, 565 0x00000080,
560 0x00000000, /* PA_SC_WINDOW_OFFSET */ 566 0x00000000, /* PA_SC_WINDOW_OFFSET */
561 567
@@ -640,31 +646,13 @@ const u32 r7xx_default_state[] =
640 0x3f800000, 646 0x3f800000,
641 647
642 0xc0016900, 648 0xc0016900,
643 0x00000293,
644 0x00514000, /* PA_SC_MODE_CNTL */
645
646 0xc0026900,
647 0x00000300,
648 0x00000000, /* PA_SC_LINE_CNTL */
649 0x00000000, /* PA_SC_AA_CONFIG */
650
651 0xc0016900,
652 0x00000312,
653 0xffffffff, /* PA_SC_AA_MASK */
654
655 0xc0026900,
656 0x00000307,
657 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
658 0x00000000,
659
660 0xc0016900,
661 0x00000283,
662 0x00000000, /* PA_SC_LINE_STIPPLE */
663
664 0xc0016900,
665 0x00000292, 649 0x00000292,
666 0x00000000, /* PA_SC_MPASS_PS_CNTL */ 650 0x00000000, /* PA_SC_MPASS_PS_CNTL */
667 651
652 0xc0016900,
653 0x00000293,
654 0x00514000, /* PA_SC_MODE_CNTL */
655
668 0xc0066900, 656 0xc0066900,
669 0x0000010f, 657 0x0000010f,
670 0x00000000, /* PA_CL_VPORT_0_XSCALE */ 658 0x00000000, /* PA_CL_VPORT_0_XSCALE */
@@ -675,9 +663,13 @@ const u32 r7xx_default_state[] =
675 0x00000000, 663 0x00000000,
676 664
677 0xc0026900, 665 0xc0026900,
678 0x00000207, 666 0x00000300,
679 0x00000000, /* PA_CL_VS_OUT_CNTL */ 667 0x00000000, /* PA_SC_LINE_CNTL */
680 0x00000000, /* PA_CL_NANINF_CNTL */ 668 0x00000000, /* PA_SC_AA_CONFIG */
669
670 0xc0016900,
671 0x00000302,
672 0x0000002d, /* PA_SU_VTX_CNTL */
681 673
682 0xc0046900, 674 0xc0046900,
683 0x00000303, 675 0x00000303,
@@ -687,45 +679,37 @@ const u32 r7xx_default_state[] =
687 0x3f800000, 679 0x3f800000,
688 680
689 0xc0026900, 681 0xc0026900,
690 0x00000280, 682 0x00000307,
691 0x00000000, /* PA_SU_POINT_SIZE */ 683 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
692 0x00000000, /* PA_SU_POINT_MINMAX */ 684 0x00000000,
685
686 0xc0016900,
687 0x00000312,
688 0xffffffff, /* PA_SC_AA_MASK */
693 689
694 0xc0016900, 690 0xc0016900,
695 0x0000037e, 691 0x0000037e,
696 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 692 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
697 693
698 0xc0016900, 694 0xc0016900,
699 0x00000382, 695 0x0000037f,
700 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ 696 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
701 697
702 0xc0016900, 698 0xc0016900,
703 0x00000380, 699 0x00000380,
704 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ 700 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
705 701
706 0xc0016900, 702 0xc0016900,
707 0x00000383,
708 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
709
710 0xc0016900,
711 0x00000381, 703 0x00000381,
712 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ 704 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
713 705
714 0xc0016900, 706 0xc0016900,
715 0x00000282, 707 0x00000382,
716 0x00000008, /* PA_SU_LINE_CNTL */ 708 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
717
718 0xc0016900,
719 0x00000302,
720 0x0000002d, /* PA_SU_VTX_CNTL */
721
722 0xc0016900,
723 0x0000037f,
724 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
725 709
726 0xc0016900, 710 0xc0016900,
727 0x000001b2, 711 0x00000383,
728 0x00000001, /* SPI_THREAD_GROUPING */ 712 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
729 713
730 0xc0046900, 714 0xc0046900,
731 0x000001b6, 715 0x000001b6,
@@ -746,28 +730,27 @@ const u32 r7xx_default_state[] =
746 0x00000237, 730 0x00000237,
747 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ 731 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
748 732
749 0xc0036900,
750 0x00000100,
751 0x00000800, /* VGT_MAX_VTX_INDX */
752 0x00000000, /* VGT_MIN_VTX_INDX */
753 0x00000000, /* VGT_INDX_OFFSET */
754
755 0xc0026900, 733 0xc0026900,
756 0x000002a8, 734 0x000002a8,
757 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 735 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
758 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ 736 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
759 737
738 0xc0026900,
739 0x00000280,
740 0x00000000, /* PA_SU_POINT_SIZE */
741 0x00000000, /* PA_SU_POINT_MINMAX */
742
760 0xc0016900, 743 0xc0016900,
761 0x00000103, 744 0x00000282,
762 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 745 0x00000008, /* PA_SU_LINE_CNTL */
763 746
764 0xc0016900, 747 0xc0016900,
765 0x00000284, 748 0x00000283,
766 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 749 0x00000000, /* PA_SC_LINE_STIPPLE */
767 750
768 0xc0016900, 751 0xc0016900,
769 0x00000290, 752 0x00000284,
770 0x00000000, /* VGT_GS_MODE */ 753 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
771 754
772 0xc00b6900, 755 0xc00b6900,
773 0x00000285, 756 0x00000285,
@@ -784,6 +767,10 @@ const u32 r7xx_default_state[] =
784 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ 767 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
785 768
786 0xc0016900, 769 0xc0016900,
770 0x00000290,
771 0x00000000, /* VGT_GS_MODE */
772
773 0xc0016900,
787 0x000002a1, 774 0x000002a1,
788 0x00000000, /* VGT_PRIMITIVEID_EN */ 775 0x00000000, /* VGT_PRIMITIVEID_EN */
789 776
@@ -802,18 +789,33 @@ const u32 r7xx_default_state[] =
802 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ 789 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
803 790
804 0xc0016900, 791 0xc0016900,
805 0x00000206, 792 0x00000202,
806 0x00000100, /* PA_CL_VTE_CNTL */ 793 0x00cc0000, /* CB_COLOR_CONTROL */
794
795 0xc0016900,
796 0x00000203,
797 0x00000210, /* DB_SHADER_CNTL */
807 798
808 0xc0016900, 799 0xc0016900,
809 0x00000204, 800 0x00000204,
810 0x00010000, /* PA_CL_CLIP_CNTL */ 801 0x00010000, /* PA_CL_CLIP_CNTL */
811 802
812 0xc0036e00, /* SET_SAMPLER */ 803 0xc0016900,
813 0x00000000, 804 0x00000205,
814 0x00000012, 805 0x00000244, /* PA_SU_SC_MODE_CNTL */
815 0x00000000, 806
816 0x00000000, 807 0xc0016900,
808 0x00000206,
809 0x00000100, /* PA_CL_VTE_CNTL */
810
811 0xc0026900,
812 0x00000207,
813 0x00000000, /* PA_CL_VS_OUT_CNTL */
814 0x00000000, /* PA_CL_NANINF_CNTL */
815
816 0xc0016900,
817 0x0000008e,
818 0x0000000f, /* CB_TARGET_MASK */
817 819
818 0xc0016900, 820 0xc0016900,
819 0x0000008f, 821 0x0000008f,
@@ -824,24 +826,20 @@ const u32 r7xx_default_state[] =
824 0x00000001, /* CB_SHADER_CONTROL */ 826 0x00000001, /* CB_SHADER_CONTROL */
825 827
826 0xc0016900, 828 0xc0016900,
827 0x00000202, 829 0x00000185,
828 0x00cc0000, /* CB_COLOR_CONTROL */ 830 0x00000000, /* SPI_VS_OUT_ID_0 */
829
830 0xc0016900,
831 0x00000205,
832 0x00000244, /* PA_SU_SC_MODE_CNTL */
833 831
834 0xc0016900, 832 0xc0016900,
835 0x00000203, 833 0x00000191,
836 0x00000210, /* DB_SHADER_CNTL */ 834 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
837 835
838 0xc0016900, 836 0xc0016900,
839 0x000001b1, 837 0x000001b1,
840 0x00000000, /* SPI_VS_OUT_CONFIG */ 838 0x00000000, /* SPI_VS_OUT_CONFIG */
841 839
842 0xc0016900, 840 0xc0016900,
843 0x00000185, 841 0x000001b2,
844 0x00000000, /* SPI_VS_OUT_ID_0 */ 842 0x00000001, /* SPI_THREAD_GROUPING */
845 843
846 0xc0026900, 844 0xc0026900,
847 0x000001b3, 845 0x000001b3,
@@ -849,12 +847,14 @@ const u32 r7xx_default_state[] =
849 0x00000000, /* SPI_PS_IN_CONTROL_1 */ 847 0x00000000, /* SPI_PS_IN_CONTROL_1 */
850 848
851 0xc0016900, 849 0xc0016900,
852 0x00000191,
853 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
854
855 0xc0016900,
856 0x000001b5, 850 0x000001b5,
857 0x00000000, /* SPI_INTERP_CONTROL_0 */ 851 0x00000000, /* SPI_INTERP_CONTROL_0 */
852
853 0xc0036e00, /* SET_SAMPLER */
854 0x00000000,
855 0x00000012,
856 0x00000000,
857 0x00000000,
858}; 858};
859 859
860/* same for r6xx/r7xx */ 860/* same for r6xx/r7xx */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 21:46:57 -0400