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authorMarc Zyngier <marc.zyngier@arm.com>2013-01-04 12:44:15 -0500
committerWill Deacon <will.deacon@arm.com>2013-01-10 16:08:55 -0500
commitd01723479e6a6c70c83295f7847477a016d5e14a (patch)
tree11daf853183da10d5177876716a4b2771e642e70
parent6e484be1ccca3ea495db45900fd42aac8d49d754 (diff)
ARM: virt: simplify __hyp_stub_install epilog
__hyp_stub_install duplicates quite a bit of safe_svcmode_maskall by forcing the CPU back to SVC. This is unnecessary, as safe_svcmode_maskall is called just after. Furthermore, the way we build SPSR_hyp is buggy as we fail to mask the interrupts, leading to interesting behaviours on TC2 + UEFI. The fix is to simply remove this code and rely on safe_svcmode_maskall to do the right thing. Cc: <stable@vger.kernel.org> Reviewed-by: Dave Martin <dave.martin@linaro.org> Reported-by: Harry Liebel <harry.liebel@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--arch/arm/kernel/hyp-stub.S12
1 files changed, 3 insertions, 9 deletions
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 3c60256d3927..1315c4ccfa56 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -120,7 +120,8 @@ ENTRY(__hyp_stub_install_secondary)
120 * Eventually, CPU-specific code might be needed -- assume not for now 120 * Eventually, CPU-specific code might be needed -- assume not for now
121 * 121 *
122 * This code relies on the "eret" instruction to synchronize the 122 * This code relies on the "eret" instruction to synchronize the
123 * various coprocessor accesses. 123 * various coprocessor accesses. This is done when we switch to SVC
124 * (see safe_svcmode_maskall).
124 */ 125 */
125 @ Now install the hypervisor stub: 126 @ Now install the hypervisor stub:
126 adr r7, __hyp_stub_vectors 127 adr r7, __hyp_stub_vectors
@@ -155,14 +156,7 @@ THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
1551: 1561:
156#endif 157#endif
157 158
158 bic r7, r4, #MODE_MASK 159 bx lr @ The boot CPU mode is left in r4.
159 orr r7, r7, #SVC_MODE
160THUMB( orr r7, r7, #PSR_T_BIT )
161 msr spsr_cxsf, r7 @ This is SPSR_hyp.
162
163 __MSR_ELR_HYP(14) @ msr elr_hyp, lr
164 __ERET @ return, switching to SVC mode
165 @ The boot CPU mode is left in r4.
166ENDPROC(__hyp_stub_install_secondary) 160ENDPROC(__hyp_stub_install_secondary)
167 161
168__hyp_stub_do_trap: 162__hyp_stub_do_trap: