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authorAndrew Murray <amurray@embedded-bits.co.uk>2013-07-25 12:14:25 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-10-29 16:24:11 -0400
commitcffe00c037cdaa14d420bb1dbc69b4dfb5f1bc23 (patch)
tree93cc96ea11a88eae9b69ee757c79daed8750d496
parent8eae19ccaeb5f519fc413c9646398a77dfbfa201 (diff)
MIPS: of/pci: Use of_pci_range_parser
This patch converts the pci_load_of_ranges function to use the new common of_pci_range_parser. Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Signed-off-by: Andrew Murray <Andrew.Murray@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: jason@lakedaemon.net Patchwork: https://patchwork.linux-mips.org/patch/5625/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/pci/pci.c50
1 files changed, 18 insertions, 32 deletions
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 33e7aa52d9c4..1bf60b127377 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -120,51 +120,37 @@ static void pcibios_scanbus(struct pci_controller *hose)
120#ifdef CONFIG_OF 120#ifdef CONFIG_OF
121void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) 121void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
122{ 122{
123 const __be32 *ranges; 123 struct of_pci_range range;
124 int rlen; 124 struct of_pci_range_parser parser;
125 int pna = of_n_addr_cells(node);
126 int np = pna + 5;
127 125
128 pr_info("PCI host bridge %s ranges:\n", node->full_name); 126 pr_info("PCI host bridge %s ranges:\n", node->full_name);
129 ranges = of_get_property(node, "ranges", &rlen);
130 if (ranges == NULL)
131 return;
132 hose->of_node = node; 127 hose->of_node = node;
133 128
134 while ((rlen -= np * 4) >= 0) { 129 if (of_pci_range_parser_init(&parser, node))
135 u32 pci_space; 130 return;
131
132 for_each_of_pci_range(&parser, &range) {
136 struct resource *res = NULL; 133 struct resource *res = NULL;
137 u64 addr, size; 134
138 135 switch (range.flags & IORESOURCE_TYPE_BITS) {
139 pci_space = be32_to_cpup(&ranges[0]); 136 case IORESOURCE_IO:
140 addr = of_translate_address(node, ranges + 3);
141 size = of_read_number(ranges + pna + 3, 2);
142 ranges += np;
143 switch ((pci_space >> 24) & 0x3) {
144 case 1: /* PCI IO space */
145 pr_info(" IO 0x%016llx..0x%016llx\n", 137 pr_info(" IO 0x%016llx..0x%016llx\n",
146 addr, addr + size - 1); 138 range.cpu_addr,
139 range.cpu_addr + range.size - 1);
147 hose->io_map_base = 140 hose->io_map_base =
148 (unsigned long)ioremap(addr, size); 141 (unsigned long)ioremap(range.cpu_addr,
142 range.size);
149 res = hose->io_resource; 143 res = hose->io_resource;
150 res->flags = IORESOURCE_IO;
151 break; 144 break;
152 case 2: /* PCI Memory space */ 145 case IORESOURCE_MEM:
153 case 3: /* PCI 64 bits Memory space */
154 pr_info(" MEM 0x%016llx..0x%016llx\n", 146 pr_info(" MEM 0x%016llx..0x%016llx\n",
155 addr, addr + size - 1); 147 range.cpu_addr,
148 range.cpu_addr + range.size - 1);
156 res = hose->mem_resource; 149 res = hose->mem_resource;
157 res->flags = IORESOURCE_MEM;
158 break; 150 break;
159 } 151 }
160 if (res != NULL) { 152 if (res != NULL)
161 res->start = addr; 153 of_pci_range_to_resource(&range, node, res);
162 res->name = node->full_name;
163 res->end = res->start + size - 1;
164 res->parent = NULL;
165 res->sibling = NULL;
166 res->child = NULL;
167 }
168 } 154 }
169} 155}
170 156