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authorEric Anholt <eric@anholt.net>2009-05-26 21:46:16 -0400
committerEric Anholt <eric@anholt.net>2009-05-26 22:11:33 -0400
commitcfa16a0de5392c54db553ec2233a7110e4b4da7a (patch)
treedece86a45e71828827ef597b1bd3363149a6d655
parente76a16deb8785317a23cca7204331af053e0fb4e (diff)
drm/i915: Apply a big hammer to 865 GEM object CPU cache flushing.
On the 865, but not the 855, the clflush we do appears to not actually make it out to the hardware all the time. An easy way to safely reproduce was X -retro, which would show that some of the blits involved in drawing the lovely root weave didn't make it out to the hardware. Those blits are 32 bytes each, and 1-2 would be missing at various points around the screen. Other experimentation (doing more clflush, doing more AGP chipset flush, poking at some more device registers to maybe trigger more flushing) didn't help. krh came up with the wbinvd as a way to successfully get all those blits to appear. Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e4408daf8cef..e2421869a40c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2423,6 +2423,16 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
2423 if (obj_priv->pages == NULL) 2423 if (obj_priv->pages == NULL)
2424 return; 2424 return;
2425 2425
2426 /* XXX: The 865 in particular appears to be weird in how it handles
2427 * cache flushing. We haven't figured it out, but the
2428 * clflush+agp_chipset_flush doesn't appear to successfully get the
2429 * data visible to the PGU, while wbinvd + agp_chipset_flush does.
2430 */
2431 if (IS_I865G(obj->dev)) {
2432 wbinvd();
2433 return;
2434 }
2435
2426 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); 2436 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2427} 2437}
2428 2438