diff options
author | Damien Lespiau <damien.lespiau@intel.com> | 2014-12-08 12:35:37 -0500 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2014-12-10 09:33:30 -0500 |
commit | cf4b0de6a3f6e1814c45206a8b175d09b265bb16 (patch) | |
tree | ddf60ce0be1046c41ed64da8d802f9813a035ced | |
parent | 98533251b0bbfa5f24c502b9ab2f01ccb25c26b8 (diff) |
drm/i915: Invert the mask and val arguments in wa_add() and WA_REG()
While trying to unify the order of those arguments throughout the
driver, Daniel noticed what we were inverting them in this part of the
code.
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 28db934b2359..ef05af02763a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -701,7 +701,7 @@ static int intel_ring_workarounds_emit(struct intel_engine_cs *ring, | |||
701 | } | 701 | } |
702 | 702 | ||
703 | static int wa_add(struct drm_i915_private *dev_priv, | 703 | static int wa_add(struct drm_i915_private *dev_priv, |
704 | const u32 addr, const u32 val, const u32 mask) | 704 | const u32 addr, const u32 mask, const u32 val) |
705 | { | 705 | { |
706 | const u32 idx = dev_priv->workarounds.count; | 706 | const u32 idx = dev_priv->workarounds.count; |
707 | 707 | ||
@@ -717,25 +717,25 @@ static int wa_add(struct drm_i915_private *dev_priv, | |||
717 | return 0; | 717 | return 0; |
718 | } | 718 | } |
719 | 719 | ||
720 | #define WA_REG(addr, val, mask) { \ | 720 | #define WA_REG(addr, mask, val) { \ |
721 | const int r = wa_add(dev_priv, (addr), (val), (mask)); \ | 721 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
722 | if (r) \ | 722 | if (r) \ |
723 | return r; \ | 723 | return r; \ |
724 | } | 724 | } |
725 | 725 | ||
726 | #define WA_SET_BIT_MASKED(addr, mask) \ | 726 | #define WA_SET_BIT_MASKED(addr, mask) \ |
727 | WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff) | 727 | WA_REG(addr, (mask) & 0xffff, _MASKED_BIT_ENABLE(mask)) |
728 | 728 | ||
729 | #define WA_CLR_BIT_MASKED(addr, mask) \ | 729 | #define WA_CLR_BIT_MASKED(addr, mask) \ |
730 | WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff) | 730 | WA_REG(addr, (mask) & 0xffff, _MASKED_BIT_DISABLE(mask)) |
731 | 731 | ||
732 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ | 732 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
733 | WA_REG(addr, _MASKED_FIELD(mask, value), mask) | 733 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
734 | 734 | ||
735 | #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask) | 735 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
736 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask) | 736 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) |
737 | 737 | ||
738 | #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff) | 738 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
739 | 739 | ||
740 | static int bdw_init_workarounds(struct intel_engine_cs *ring) | 740 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
741 | { | 741 | { |