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authorBen Skeggs <bskeggs@redhat.com>2014-01-14 00:55:38 -0500
committerBen Skeggs <bskeggs@redhat.com>2014-01-22 22:39:12 -0500
commitcf336014c6dc3ef1431d84b5a94e47a22660493b (patch)
tree150e3087901cd03435775ece8baf55ffc072813d
parent52225551ddcae9c4df6c48bc3c78833aac5074f4 (diff)
drm/nouveau/devinit: tidy up the subdev class definition
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv04.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv10.c16
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv20.c8
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv30.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv40.c32
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nv50.c28
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nvc0.c18
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/devinit.h36
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/base.c6
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c23
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h23
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c41
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c41
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c37
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c41
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c16
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h15
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c34
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c16
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h35
22 files changed, 209 insertions, 283 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
index a50d1b468f76..32113b08c4d5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c
@@ -49,7 +49,7 @@ nv04_identify(struct nouveau_device *device)
49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 50 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
52 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass; 52 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
53 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 53 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
54 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 54 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -67,7 +67,7 @@ nv04_identify(struct nouveau_device *device)
67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
68 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 68 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
70 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass; 70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
71 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 71 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
72 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 72 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
index 1541a97a1a15..744f15d7e131 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c
@@ -51,7 +51,7 @@ nv10_identify(struct nouveau_device *device)
51 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 51 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
52 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 52 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
53 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 53 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
54 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 54 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
55 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 55 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
56 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 56 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
57 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 57 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -68,7 +68,7 @@ nv10_identify(struct nouveau_device *device)
68 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 68 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
69 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 69 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
70 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 70 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
71 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
72 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 72 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
73 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 73 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -87,7 +87,7 @@ nv10_identify(struct nouveau_device *device)
87 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 87 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
88 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 88 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
90 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 90 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
91 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 91 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
92 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 92 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
93 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 93 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -106,7 +106,7 @@ nv10_identify(struct nouveau_device *device)
106 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 106 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
107 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 107 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
108 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 108 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
109 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 109 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
110 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 110 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
111 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 111 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -125,7 +125,7 @@ nv10_identify(struct nouveau_device *device)
125 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 125 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
126 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 126 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
128 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 128 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
129 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 129 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
130 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 130 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -144,7 +144,7 @@ nv10_identify(struct nouveau_device *device)
144 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 144 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
145 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 145 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
146 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 146 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
147 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 147 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
148 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 148 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
149 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 149 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -163,7 +163,7 @@ nv10_identify(struct nouveau_device *device)
163 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 163 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
164 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 164 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
166 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 166 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
167 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 167 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
168 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 168 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -182,7 +182,7 @@ nv10_identify(struct nouveau_device *device)
182 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 182 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
183 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 183 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
184 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 184 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
185 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 185 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
186 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 186 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
187 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 187 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
index d47ba090b32f..27ba61fb2710 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c
@@ -52,7 +52,7 @@ nv20_identify(struct nouveau_device *device)
52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
53 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 55 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -71,7 +71,7 @@ nv20_identify(struct nouveau_device *device)
71 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 71 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
72 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 72 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
74 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 74 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -90,7 +90,7 @@ nv20_identify(struct nouveau_device *device)
90 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 90 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
91 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 91 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
93 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
95 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -109,7 +109,7 @@ nv20_identify(struct nouveau_device *device)
109 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 109 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
110 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 110 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
112 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 112 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
113 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 113 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
114 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 114 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
115 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 115 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
index 86a4ec73377c..fd47ace67543 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c
@@ -52,7 +52,7 @@ nv30_identify(struct nouveau_device *device)
52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
53 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 55 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -71,7 +71,7 @@ nv30_identify(struct nouveau_device *device)
71 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 71 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
72 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 72 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
74 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 74 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -90,7 +90,7 @@ nv30_identify(struct nouveau_device *device)
90 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 90 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
91 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 91 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 92 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
93 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
95 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -110,7 +110,7 @@ nv30_identify(struct nouveau_device *device)
110 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 110 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
111 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 111 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
112 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 112 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
113 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; 113 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
114 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 114 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
115 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 115 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
116 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 116 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -130,7 +130,7 @@ nv30_identify(struct nouveau_device *device)
130 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 130 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
131 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 131 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
132 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 132 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
133 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; 133 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
134 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 134 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
135 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 135 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
index 688257bd0cc0..1b653dd74a70 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c
@@ -57,7 +57,7 @@ nv40_identify(struct nouveau_device *device)
57 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 57 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
58 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 58 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
59 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 59 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
60 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 60 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
61 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 61 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
62 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 62 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
63 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 63 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -80,7 +80,7 @@ nv40_identify(struct nouveau_device *device)
80 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 80 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
82 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 82 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
83 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 83 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
84 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 84 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
85 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 85 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -103,7 +103,7 @@ nv40_identify(struct nouveau_device *device)
103 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 103 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
104 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 104 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
105 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 105 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
106 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 106 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
107 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 107 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
108 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 108 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
109 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 109 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -126,7 +126,7 @@ nv40_identify(struct nouveau_device *device)
126 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 126 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
128 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 128 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
129 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 129 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
130 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 130 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
131 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 131 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
132 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 132 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -149,7 +149,7 @@ nv40_identify(struct nouveau_device *device)
149 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 149 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
150 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 150 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
151 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 151 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
152 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 152 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
153 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 153 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
154 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 154 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
155 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 155 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -172,7 +172,7 @@ nv40_identify(struct nouveau_device *device)
172 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 172 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
173 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 173 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
174 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 174 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
175 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 175 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
176 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 176 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
177 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 177 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
178 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 178 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -195,7 +195,7 @@ nv40_identify(struct nouveau_device *device)
195 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 195 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
196 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 196 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
197 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 197 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
198 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 198 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
199 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 199 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
200 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 200 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
201 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 201 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -218,7 +218,7 @@ nv40_identify(struct nouveau_device *device)
218 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 218 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
219 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 219 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
220 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 220 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
221 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 221 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
222 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; 222 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
223 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 223 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
224 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 224 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -241,7 +241,7 @@ nv40_identify(struct nouveau_device *device)
241 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 241 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
242 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 242 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
243 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 243 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
244 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 244 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
245 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 245 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
246 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 246 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -264,7 +264,7 @@ nv40_identify(struct nouveau_device *device)
264 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 264 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
265 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 265 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
266 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 266 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
267 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 267 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
268 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 268 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
269 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 269 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
270 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 270 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -287,7 +287,7 @@ nv40_identify(struct nouveau_device *device)
287 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 287 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
288 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 288 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
289 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 289 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
290 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 290 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
291 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 291 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
292 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 292 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -310,7 +310,7 @@ nv40_identify(struct nouveau_device *device)
310 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 310 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
311 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 311 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
312 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 312 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
313 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 313 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
314 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 314 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
315 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 315 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
316 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 316 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -333,7 +333,7 @@ nv40_identify(struct nouveau_device *device)
333 device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass; 333 device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass;
334 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 334 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
336 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 336 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
337 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 337 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
338 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 338 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -356,7 +356,7 @@ nv40_identify(struct nouveau_device *device)
356 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 356 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
357 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 357 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
358 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 358 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
359 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 359 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
360 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 360 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
361 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 361 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
362 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 362 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -379,7 +379,7 @@ nv40_identify(struct nouveau_device *device)
379 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 379 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
380 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 380 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
381 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 381 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
382 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 382 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
383 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 383 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
384 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 384 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
385 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 385 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -402,7 +402,7 @@ nv40_identify(struct nouveau_device *device)
402 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; 402 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
403 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 403 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
404 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; 404 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
405 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; 405 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
406 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; 406 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
407 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; 407 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
index 5ee426985d45..5ae94475a3f1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
@@ -65,7 +65,7 @@ nv50_identify(struct nouveau_device *device)
65 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; 65 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass;
66 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; 66 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
68 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 68 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
69 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; 69 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
70 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; 70 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -90,7 +90,7 @@ nv50_identify(struct nouveau_device *device)
90 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 90 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
91 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 91 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
92 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 92 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
93 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
94 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; 94 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
95 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -118,7 +118,7 @@ nv50_identify(struct nouveau_device *device)
118 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 118 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
119 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 119 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
120 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 120 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
121 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 121 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
122 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; 122 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
123 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; 123 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -146,7 +146,7 @@ nv50_identify(struct nouveau_device *device)
146 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 146 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
147 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 147 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
148 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 148 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
149 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 149 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
150 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; 150 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
151 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; 151 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
152 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 152 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -174,7 +174,7 @@ nv50_identify(struct nouveau_device *device)
174 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 174 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
175 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 175 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
176 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 176 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
177 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 177 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
178 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; 178 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
179 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 179 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
180 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 180 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -202,7 +202,7 @@ nv50_identify(struct nouveau_device *device)
202 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 202 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
203 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 203 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
204 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 204 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
205 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 205 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
206 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; 206 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
207 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 207 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -230,7 +230,7 @@ nv50_identify(struct nouveau_device *device)
230 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 230 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
231 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 231 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
232 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 232 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
233 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 233 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
234 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 234 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
235 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 235 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
236 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 236 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -258,7 +258,7 @@ nv50_identify(struct nouveau_device *device)
258 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; 258 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
259 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 259 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
260 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 260 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
261 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 261 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
262 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 262 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
263 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 263 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
264 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 264 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -286,7 +286,7 @@ nv50_identify(struct nouveau_device *device)
286 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; 286 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
287 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 287 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
288 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 288 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
289 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 289 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
290 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 290 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
291 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 291 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
292 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 292 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -314,7 +314,7 @@ nv50_identify(struct nouveau_device *device)
314 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; 314 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
315 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; 315 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
316 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 316 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
317 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; 317 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
318 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 318 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
319 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 319 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
320 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 320 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -342,7 +342,7 @@ nv50_identify(struct nouveau_device *device)
342 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 342 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
343 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 343 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
344 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 344 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
345 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; 345 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
346 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 346 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
347 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 347 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
348 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 348 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -372,7 +372,7 @@ nv50_identify(struct nouveau_device *device)
372 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 372 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
373 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 373 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
374 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 374 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
375 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; 375 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
376 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 376 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
377 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 377 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
378 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 378 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -401,7 +401,7 @@ nv50_identify(struct nouveau_device *device)
401 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 401 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
402 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 402 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
403 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 403 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
404 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; 404 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
405 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 405 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
406 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 406 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
407 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 407 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -430,7 +430,7 @@ nv50_identify(struct nouveau_device *device)
430 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 430 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
431 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 431 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
432 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 432 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
433 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; 433 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
434 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; 434 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
435 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; 435 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
436 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 436 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index f3d634e32590..b7d66b59f43d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -65,7 +65,7 @@ nvc0_identify(struct nouveau_device *device)
65 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 65 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
66 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 66 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
68 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 68 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
69 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; 69 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -97,7 +97,7 @@ nvc0_identify(struct nouveau_device *device)
97 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 97 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
98 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 98 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
99 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 99 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
100 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 100 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
101 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; 101 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
102 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 102 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
103 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 103 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -129,7 +129,7 @@ nvc0_identify(struct nouveau_device *device)
129 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 129 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
130 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 130 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
131 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 131 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
132 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 132 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
133 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 133 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
134 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 134 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
135 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 135 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -160,7 +160,7 @@ nvc0_identify(struct nouveau_device *device)
160 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 160 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
161 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 161 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
162 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 162 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
163 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 163 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
164 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; 164 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
165 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 165 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -192,7 +192,7 @@ nvc0_identify(struct nouveau_device *device)
192 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 192 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
193 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 193 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
194 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 194 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
195 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 195 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
196 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 196 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
197 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 197 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
198 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 198 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -224,7 +224,7 @@ nvc0_identify(struct nouveau_device *device)
224 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 224 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
225 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 225 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
226 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 226 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
227 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 227 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
228 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 228 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
229 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 229 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
230 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 230 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -255,7 +255,7 @@ nvc0_identify(struct nouveau_device *device)
255 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 255 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
256 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; 256 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
257 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 257 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
258 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 258 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
259 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; 259 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
260 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 260 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
261 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 261 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -287,7 +287,7 @@ nvc0_identify(struct nouveau_device *device)
287 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 287 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
288 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 288 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
289 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 289 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
290 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 290 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
291 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 291 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
292 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 292 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -318,7 +318,7 @@ nvc0_identify(struct nouveau_device *device)
318 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 318 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
319 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 319 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
320 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 320 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
321 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 321 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
322 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 322 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
323 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 323 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
324 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 324 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index a370e9ed2085..987edbc30a09 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -65,7 +65,7 @@ nve0_identify(struct nouveau_device *device)
65 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 65 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
66 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 66 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
68 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 68 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
69 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 69 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -98,7 +98,7 @@ nve0_identify(struct nouveau_device *device)
98 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 98 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
99 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 99 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
100 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 100 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
101 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 101 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
102 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 102 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
103 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 103 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
104 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 104 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -131,7 +131,7 @@ nve0_identify(struct nouveau_device *device)
131 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 131 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
132 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 132 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
133 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 133 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
134 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 134 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
135 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 135 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
136 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 136 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
137 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 137 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -164,7 +164,7 @@ nve0_identify(struct nouveau_device *device)
164 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 164 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
165 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 165 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
166 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 166 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
167 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 167 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
168 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 168 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
169 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 169 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
170 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 170 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
@@ -199,7 +199,7 @@ nve0_identify(struct nouveau_device *device)
199 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; 199 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
200 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 200 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
201 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 201 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
202 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; 202 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
203 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; 203 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
204 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; 204 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
205 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 205 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
index 685c9b12ee4c..e59384d04870 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
@@ -9,7 +9,6 @@ struct nouveau_devinit {
9 bool post; 9 bool post;
10 void (*meminit)(struct nouveau_devinit *); 10 void (*meminit)(struct nouveau_devinit *);
11 int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq); 11 int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq);
12
13}; 12};
14 13
15static inline struct nouveau_devinit * 14static inline struct nouveau_devinit *
@@ -18,32 +17,13 @@ nouveau_devinit(void *obj)
18 return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT]; 17 return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT];
19} 18}
20 19
21#define nouveau_devinit_create(p,e,o,d) \ 20extern struct nouveau_oclass *nv04_devinit_oclass;
22 nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d) 21extern struct nouveau_oclass *nv05_devinit_oclass;
23#define nouveau_devinit_destroy(p) \ 22extern struct nouveau_oclass *nv10_devinit_oclass;
24 nouveau_subdev_destroy(&(p)->base) 23extern struct nouveau_oclass *nv1a_devinit_oclass;
25#define nouveau_devinit_init(p) ({ \ 24extern struct nouveau_oclass *nv20_devinit_oclass;
26 struct nouveau_devinit *d = (p); \ 25extern struct nouveau_oclass *nv50_devinit_oclass;
27 _nouveau_devinit_init(nv_object(d)); \ 26extern struct nouveau_oclass *nva3_devinit_oclass;
28}) 27extern struct nouveau_oclass *nvc0_devinit_oclass;
29#define nouveau_devinit_fini(p,s) ({ \
30 struct nouveau_devinit *d = (p); \
31 _nouveau_devinit_fini(nv_object(d), (s)); \
32})
33
34int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *,
35 struct nouveau_oclass *, int, void **);
36#define _nouveau_devinit_dtor _nouveau_subdev_dtor
37int _nouveau_devinit_init(struct nouveau_object *);
38int _nouveau_devinit_fini(struct nouveau_object *, bool suspend);
39
40extern struct nouveau_oclass nv04_devinit_oclass;
41extern struct nouveau_oclass nv05_devinit_oclass;
42extern struct nouveau_oclass nv10_devinit_oclass;
43extern struct nouveau_oclass nv1a_devinit_oclass;
44extern struct nouveau_oclass nv20_devinit_oclass;
45extern struct nouveau_oclass nv50_devinit_oclass;
46extern struct nouveau_oclass nva3_devinit_oclass;
47extern struct nouveau_oclass nvc0_devinit_oclass;
48 28
49#endif 29#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
index 30c1f3a4158e..b74db6cfc4e2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
@@ -25,7 +25,7 @@
25#include <subdev/bios.h> 25#include <subdev/bios.h>
26#include <subdev/bios/pll.h> 26#include <subdev/bios/pll.h>
27#include <subdev/clock.h> 27#include <subdev/clock.h>
28#include <subdev/devinit/priv.h> 28#include <subdev/devinit/nv04.h>
29 29
30#include "pll.h" 30#include "pll.h"
31 31
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
index 79c81d3d9bac..6013c42503d1 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
@@ -24,10 +24,11 @@
24 24
25#include <core/option.h> 25#include <core/option.h>
26 26
27#include <subdev/devinit.h>
28#include <subdev/bios.h> 27#include <subdev/bios.h>
29#include <subdev/bios/init.h> 28#include <subdev/bios/init.h>
30 29
30#include "priv.h"
31
31int 32int
32_nouveau_devinit_fini(struct nouveau_object *object, bool suspend) 33_nouveau_devinit_fini(struct nouveau_object *object, bool suspend)
33{ 34{
@@ -57,6 +58,7 @@ nouveau_devinit_create_(struct nouveau_object *parent,
57 struct nouveau_oclass *oclass, 58 struct nouveau_oclass *oclass,
58 int size, void **pobject) 59 int size, void **pobject)
59{ 60{
61 struct nouveau_devinit_impl *impl = (void *)oclass;
60 struct nouveau_device *device = nv_device(parent); 62 struct nouveau_device *device = nv_device(parent);
61 struct nouveau_devinit *devinit; 63 struct nouveau_devinit *devinit;
62 int ret; 64 int ret;
@@ -68,5 +70,7 @@ nouveau_devinit_create_(struct nouveau_object *parent,
68 return ret; 70 return ret;
69 71
70 devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false); 72 devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false);
73 devinit->meminit = impl->meminit;
74 devinit->pll_set = impl->pll_set;
71 return 0; 75 return 0;
72} 76}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
index 27c8235f1a85..24025e4e882a 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
@@ -27,12 +27,7 @@
27#include <subdev/vga.h> 27#include <subdev/vga.h>
28 28
29#include "fbmem.h" 29#include "fbmem.h"
30#include "priv.h" 30#include "nv04.h"
31
32struct nv04_devinit_priv {
33 struct nouveau_devinit base;
34 int owner;
35};
36 31
37static void 32static void
38nv04_devinit_meminit(struct nouveau_devinit *devinit) 33nv04_devinit_meminit(struct nouveau_devinit *devinit)
@@ -438,7 +433,7 @@ nv04_devinit_dtor(struct nouveau_object *object)
438 nouveau_devinit_destroy(&priv->base); 433 nouveau_devinit_destroy(&priv->base);
439} 434}
440 435
441static int 436int
442nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 437nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
443 struct nouveau_oclass *oclass, void *data, u32 size, 438 struct nouveau_oclass *oclass, void *data, u32 size,
444 struct nouveau_object **pobject) 439 struct nouveau_object **pobject)
@@ -451,19 +446,19 @@ nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
451 if (ret) 446 if (ret)
452 return ret; 447 return ret;
453 448
454 priv->base.meminit = nv04_devinit_meminit;
455 priv->base.pll_set = nv04_devinit_pll_set;
456 priv->owner = -1; 449 priv->owner = -1;
457 return 0; 450 return 0;
458} 451}
459 452
460struct nouveau_oclass 453struct nouveau_oclass *
461nv04_devinit_oclass = { 454nv04_devinit_oclass = &(struct nouveau_devinit_impl) {
462 .handle = NV_SUBDEV(DEVINIT, 0x04), 455 .base.handle = NV_SUBDEV(DEVINIT, 0x04),
463 .ofuncs = &(struct nouveau_ofuncs) { 456 .base.ofuncs = &(struct nouveau_ofuncs) {
464 .ctor = nv04_devinit_ctor, 457 .ctor = nv04_devinit_ctor,
465 .dtor = nv04_devinit_dtor, 458 .dtor = nv04_devinit_dtor,
466 .init = nv04_devinit_init, 459 .init = nv04_devinit_init,
467 .fini = nv04_devinit_fini, 460 .fini = nv04_devinit_fini,
468 }, 461 },
469}; 462 .meminit = nv04_devinit_meminit,
463 .pll_set = nv04_devinit_pll_set,
464}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h
new file mode 100644
index 000000000000..23470a57510c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h
@@ -0,0 +1,23 @@
1#ifndef __NVKM_DEVINIT_NV04_H__
2#define __NVKM_DEVINIT_NV04_H__
3
4#include "priv.h"
5
6struct nv04_devinit_priv {
7 struct nouveau_devinit base;
8 u8 owner;
9};
10
11int nv04_devinit_ctor(struct nouveau_object *, struct nouveau_object *,
12 struct nouveau_oclass *, void *, u32,
13 struct nouveau_object **);
14void nv04_devinit_dtor(struct nouveau_object *);
15int nv04_devinit_init(struct nouveau_object *);
16int nv04_devinit_fini(struct nouveau_object *, bool);
17int nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32);
18
19void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
20void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
21void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
22
23#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
index b1912a8a8942..98b7e6780dc7 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
@@ -29,12 +29,7 @@
29#include <subdev/vga.h> 29#include <subdev/vga.h>
30 30
31#include "fbmem.h" 31#include "fbmem.h"
32#include "priv.h" 32#include "nv04.h"
33
34struct nv05_devinit_priv {
35 struct nouveau_devinit base;
36 u8 owner;
37};
38 33
39static void 34static void
40nv05_devinit_meminit(struct nouveau_devinit *devinit) 35nv05_devinit_meminit(struct nouveau_devinit *devinit)
@@ -49,7 +44,7 @@ nv05_devinit_meminit(struct nouveau_devinit *devinit)
49 { 0x06, 0x00 }, 44 { 0x06, 0x00 },
50 { 0x00, 0x00 } 45 { 0x00, 0x00 }
51 }; 46 };
52 struct nv05_devinit_priv *priv = (void *)devinit; 47 struct nv04_devinit_priv *priv = (void *)devinit;
53 struct nouveau_bios *bios = nouveau_bios(priv); 48 struct nouveau_bios *bios = nouveau_bios(priv);
54 struct io_mapping *fb; 49 struct io_mapping *fb;
55 u32 patt = 0xdeadbeef; 50 u32 patt = 0xdeadbeef;
@@ -130,31 +125,15 @@ out:
130 fbmem_fini(fb); 125 fbmem_fini(fb);
131} 126}
132 127
133static int 128struct nouveau_oclass *
134nv05_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 129nv05_devinit_oclass = &(struct nouveau_devinit_impl) {
135 struct nouveau_oclass *oclass, void *data, u32 size, 130 .base.handle = NV_SUBDEV(DEVINIT, 0x05),
136 struct nouveau_object **pobject) 131 .base.ofuncs = &(struct nouveau_ofuncs) {
137{ 132 .ctor = nv04_devinit_ctor,
138 struct nv05_devinit_priv *priv;
139 int ret;
140
141 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
142 *pobject = nv_object(priv);
143 if (ret)
144 return ret;
145
146 priv->base.meminit = nv05_devinit_meminit;
147 priv->base.pll_set = nv04_devinit_pll_set;
148 return 0;
149}
150
151struct nouveau_oclass
152nv05_devinit_oclass = {
153 .handle = NV_SUBDEV(DEVINIT, 0x05),
154 .ofuncs = &(struct nouveau_ofuncs) {
155 .ctor = nv05_devinit_ctor,
156 .dtor = nv04_devinit_dtor, 133 .dtor = nv04_devinit_dtor,
157 .init = nv04_devinit_init, 134 .init = nv04_devinit_init,
158 .fini = nv04_devinit_fini, 135 .fini = nv04_devinit_fini,
159 }, 136 },
160}; 137 .meminit = nv05_devinit_meminit,
138 .pll_set = nv04_devinit_pll_set,
139}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
index 8d274dba1ef1..32b3d2131a7f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
@@ -27,17 +27,12 @@
27#include <subdev/vga.h> 27#include <subdev/vga.h>
28 28
29#include "fbmem.h" 29#include "fbmem.h"
30#include "priv.h" 30#include "nv04.h"
31
32struct nv10_devinit_priv {
33 struct nouveau_devinit base;
34 u8 owner;
35};
36 31
37static void 32static void
38nv10_devinit_meminit(struct nouveau_devinit *devinit) 33nv10_devinit_meminit(struct nouveau_devinit *devinit)
39{ 34{
40 struct nv10_devinit_priv *priv = (void *)devinit; 35 struct nv04_devinit_priv *priv = (void *)devinit;
41 static const int mem_width[] = { 0x10, 0x00, 0x20 }; 36 static const int mem_width[] = { 0x10, 0x00, 0x20 };
42 int mem_width_count; 37 int mem_width_count;
43 uint32_t patt = 0xdeadbeef; 38 uint32_t patt = 0xdeadbeef;
@@ -101,31 +96,15 @@ amount_found:
101 fbmem_fini(fb); 96 fbmem_fini(fb);
102} 97}
103 98
104static int 99struct nouveau_oclass *
105nv10_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 100nv10_devinit_oclass = &(struct nouveau_devinit_impl) {
106 struct nouveau_oclass *oclass, void *data, u32 size, 101 .base.handle = NV_SUBDEV(DEVINIT, 0x10),
107 struct nouveau_object **pobject) 102 .base.ofuncs = &(struct nouveau_ofuncs) {
108{ 103 .ctor = nv04_devinit_ctor,
109 struct nv10_devinit_priv *priv;
110 int ret;
111
112 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
113 *pobject = nv_object(priv);
114 if (ret)
115 return ret;
116
117 priv->base.meminit = nv10_devinit_meminit;
118 priv->base.pll_set = nv04_devinit_pll_set;
119 return 0;
120}
121
122struct nouveau_oclass
123nv10_devinit_oclass = {
124 .handle = NV_SUBDEV(DEVINIT, 0x10),
125 .ofuncs = &(struct nouveau_ofuncs) {
126 .ctor = nv10_devinit_ctor,
127 .dtor = nv04_devinit_dtor, 104 .dtor = nv04_devinit_dtor,
128 .init = nv04_devinit_init, 105 .init = nv04_devinit_init,
129 .fini = nv04_devinit_fini, 106 .fini = nv04_devinit_fini,
130 }, 107 },
131}; 108 .meminit = nv10_devinit_meminit,
109 .pll_set = nv04_devinit_pll_set,
110}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
index e9743cdabe75..526d0c6faacd 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
@@ -22,37 +22,16 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include "priv.h" 25#include "nv04.h"
26 26
27struct nv1a_devinit_priv { 27struct nouveau_oclass *
28 struct nouveau_devinit base; 28nv1a_devinit_oclass = &(struct nouveau_devinit_impl) {
29 u8 owner; 29 .base.handle = NV_SUBDEV(DEVINIT, 0x1a),
30}; 30 .base.ofuncs = &(struct nouveau_ofuncs) {
31 31 .ctor = nv04_devinit_ctor,
32static int
33nv1a_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
34 struct nouveau_oclass *oclass, void *data, u32 size,
35 struct nouveau_object **pobject)
36{
37 struct nv1a_devinit_priv *priv;
38 int ret;
39
40 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
41 *pobject = nv_object(priv);
42 if (ret)
43 return ret;
44
45 priv->base.pll_set = nv04_devinit_pll_set;
46 return 0;
47}
48
49struct nouveau_oclass
50nv1a_devinit_oclass = {
51 .handle = NV_SUBDEV(DEVINIT, 0x1a),
52 .ofuncs = &(struct nouveau_ofuncs) {
53 .ctor = nv1a_devinit_ctor,
54 .dtor = nv04_devinit_dtor, 32 .dtor = nv04_devinit_dtor,
55 .init = nv04_devinit_init, 33 .init = nv04_devinit_init,
56 .fini = nv04_devinit_fini, 34 .fini = nv04_devinit_fini,
57 }, 35 },
58}; 36 .pll_set = nv04_devinit_pll_set,
37}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
index 6cc6080d3bc0..4689ba303b0b 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
@@ -24,18 +24,13 @@
24 * 24 *
25 */ 25 */
26 26
27#include "priv.h" 27#include "nv04.h"
28#include "fbmem.h" 28#include "fbmem.h"
29 29
30struct nv20_devinit_priv {
31 struct nouveau_devinit base;
32 u8 owner;
33};
34
35static void 30static void
36nv20_devinit_meminit(struct nouveau_devinit *devinit) 31nv20_devinit_meminit(struct nouveau_devinit *devinit)
37{ 32{
38 struct nv20_devinit_priv *priv = (void *)devinit; 33 struct nv04_devinit_priv *priv = (void *)devinit;
39 struct nouveau_device *device = nv_device(priv); 34 struct nouveau_device *device = nv_device(priv);
40 uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900); 35 uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900);
41 uint32_t amount, off; 36 uint32_t amount, off;
@@ -65,31 +60,15 @@ nv20_devinit_meminit(struct nouveau_devinit *devinit)
65 fbmem_fini(fb); 60 fbmem_fini(fb);
66} 61}
67 62
68static int 63struct nouveau_oclass *
69nv20_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 64nv20_devinit_oclass = &(struct nouveau_devinit_impl) {
70 struct nouveau_oclass *oclass, void *data, u32 size, 65 .base.handle = NV_SUBDEV(DEVINIT, 0x20),
71 struct nouveau_object **pobject) 66 .base.ofuncs = &(struct nouveau_ofuncs) {
72{ 67 .ctor = nv04_devinit_ctor,
73 struct nv20_devinit_priv *priv;
74 int ret;
75
76 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
77 *pobject = nv_object(priv);
78 if (ret)
79 return ret;
80
81 priv->base.meminit = nv20_devinit_meminit;
82 priv->base.pll_set = nv04_devinit_pll_set;
83 return 0;
84}
85
86struct nouveau_oclass
87nv20_devinit_oclass = {
88 .handle = NV_SUBDEV(DEVINIT, 0x20),
89 .ofuncs = &(struct nouveau_ofuncs) {
90 .ctor = nv20_devinit_ctor,
91 .dtor = nv04_devinit_dtor, 68 .dtor = nv04_devinit_dtor,
92 .init = nv04_devinit_init, 69 .init = nv04_devinit_init,
93 .fini = nv04_devinit_fini, 70 .fini = nv04_devinit_fini,
94 }, 71 },
95}; 72 .meminit = nv20_devinit_meminit,
73 .pll_set = nv04_devinit_pll_set,
74}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
index 6df72247c477..f81509eb6c3e 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
@@ -28,7 +28,7 @@
28#include <subdev/bios/init.h> 28#include <subdev/bios/init.h>
29#include <subdev/vga.h> 29#include <subdev/vga.h>
30 30
31#include "priv.h" 31#include "nv50.h"
32 32
33static int 33static int
34nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) 34nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
@@ -120,7 +120,7 @@ nv50_devinit_init(struct nouveau_object *object)
120 return 0; 120 return 0;
121} 121}
122 122
123static int 123int
124nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 124nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
125 struct nouveau_oclass *oclass, void *data, u32 size, 125 struct nouveau_oclass *oclass, void *data, u32 size,
126 struct nouveau_object **pobject) 126 struct nouveau_object **pobject)
@@ -133,17 +133,17 @@ nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
133 if (ret) 133 if (ret)
134 return ret; 134 return ret;
135 135
136 priv->base.pll_set = nv50_devinit_pll_set;
137 return 0; 136 return 0;
138} 137}
139 138
140struct nouveau_oclass 139struct nouveau_oclass *
141nv50_devinit_oclass = { 140nv50_devinit_oclass = &(struct nouveau_devinit_impl) {
142 .handle = NV_SUBDEV(DEVINIT, 0x50), 141 .base.handle = NV_SUBDEV(DEVINIT, 0x50),
143 .ofuncs = &(struct nouveau_ofuncs) { 142 .base.ofuncs = &(struct nouveau_ofuncs) {
144 .ctor = nv50_devinit_ctor, 143 .ctor = nv50_devinit_ctor,
145 .dtor = _nouveau_devinit_dtor, 144 .dtor = _nouveau_devinit_dtor,
146 .init = nv50_devinit_init, 145 .init = nv50_devinit_init,
147 .fini = _nouveau_devinit_fini, 146 .fini = _nouveau_devinit_fini,
148 }, 147 },
149}; 148 .pll_set = nv50_devinit_pll_set,
149}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h
new file mode 100644
index 000000000000..f87e483b0977
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h
@@ -0,0 +1,15 @@
1#ifndef __NVKM_DEVINIT_NV50_H__
2#define __NVKM_DEVINIT_NV50_H__
3
4#include "priv.h"
5
6struct nv50_devinit_priv {
7 struct nouveau_devinit base;
8};
9
10int nv50_devinit_ctor(struct nouveau_object *, struct nouveau_object *,
11 struct nouveau_oclass *, void *, u32,
12 struct nouveau_object **);
13int nv50_devinit_init(struct nouveau_object *);
14
15#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c
index 76a68b290141..67f55940b00e 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c
@@ -22,12 +22,12 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include "priv.h" 25#include "nv50.h"
26 26
27static int 27static int
28nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) 28nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
29{ 29{
30 struct nva3_devinit_priv *priv = (void *)devinit; 30 struct nv50_devinit_priv *priv = (void *)devinit;
31 struct nouveau_bios *bios = nouveau_bios(priv); 31 struct nouveau_bios *bios = nouveau_bios(priv);
32 struct nvbios_pll info; 32 struct nvbios_pll info;
33 int N, fN, M, P; 33 int N, fN, M, P;
@@ -58,30 +58,14 @@ nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
58 return ret; 58 return ret;
59} 59}
60 60
61static int 61struct nouveau_oclass *
62nva3_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 62nva3_devinit_oclass = &(struct nouveau_devinit_impl) {
63 struct nouveau_oclass *oclass, void *data, u32 size, 63 .base.handle = NV_SUBDEV(DEVINIT, 0xa3),
64 struct nouveau_object **pobject) 64 .base.ofuncs = &(struct nouveau_ofuncs) {
65{ 65 .ctor = nv50_devinit_ctor,
66 struct nv50_devinit_priv *priv;
67 int ret;
68
69 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
70 *pobject = nv_object(priv);
71 if (ret)
72 return ret;
73
74 priv->base.pll_set = nva3_devinit_pll_set;
75 return 0;
76}
77
78struct nouveau_oclass
79nva3_devinit_oclass = {
80 .handle = NV_SUBDEV(DEVINIT, 0xa3),
81 .ofuncs = &(struct nouveau_ofuncs) {
82 .ctor = nva3_devinit_ctor,
83 .dtor = _nouveau_devinit_dtor, 66 .dtor = _nouveau_devinit_dtor,
84 .init = nv50_devinit_init, 67 .init = nv50_devinit_init,
85 .fini = _nouveau_devinit_fini, 68 .fini = _nouveau_devinit_fini,
86 }, 69 },
87}; 70 .pll_set = nva3_devinit_pll_set,
71}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
index 19e265bf4574..ced0e8241b34 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
@@ -22,12 +22,12 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include "priv.h" 25#include "nv50.h"
26 26
27static int 27static int
28nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) 28nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
29{ 29{
30 struct nvc0_devinit_priv *priv = (void *)devinit; 30 struct nv50_devinit_priv *priv = (void *)devinit;
31 struct nouveau_bios *bios = nouveau_bios(priv); 31 struct nouveau_bios *bios = nouveau_bios(priv);
32 struct nvbios_pll info; 32 struct nvbios_pll info;
33 int N, fN, M, P; 33 int N, fN, M, P;
@@ -72,19 +72,19 @@ nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
72 if (ret) 72 if (ret)
73 return ret; 73 return ret;
74 74
75 priv->base.pll_set = nvc0_devinit_pll_set;
76 if (nv_rd32(priv, 0x022500) & 0x00000001) 75 if (nv_rd32(priv, 0x022500) & 0x00000001)
77 priv->base.post = true; 76 priv->base.post = true;
78 return 0; 77 return 0;
79} 78}
80 79
81struct nouveau_oclass 80struct nouveau_oclass *
82nvc0_devinit_oclass = { 81nvc0_devinit_oclass = &(struct nouveau_devinit_impl) {
83 .handle = NV_SUBDEV(DEVINIT, 0xc0), 82 .base.handle = NV_SUBDEV(DEVINIT, 0xc0),
84 .ofuncs = &(struct nouveau_ofuncs) { 83 .base.ofuncs = &(struct nouveau_ofuncs) {
85 .ctor = nvc0_devinit_ctor, 84 .ctor = nvc0_devinit_ctor,
86 .dtor = _nouveau_devinit_dtor, 85 .dtor = _nouveau_devinit_dtor,
87 .init = nv50_devinit_init, 86 .init = nv50_devinit_init,
88 .fini = _nouveau_devinit_fini, 87 .fini = _nouveau_devinit_fini,
89 }, 88 },
90}; 89 .pll_set = nvc0_devinit_pll_set,
90}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h
index 7d622e2b0171..ae8de97ecf16 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h
@@ -6,20 +6,29 @@
6#include <subdev/clock/pll.h> 6#include <subdev/clock/pll.h>
7#include <subdev/devinit.h> 7#include <subdev/devinit.h>
8 8
9void nv04_devinit_dtor(struct nouveau_object *); 9struct nouveau_devinit_impl {
10int nv04_devinit_init(struct nouveau_object *); 10 struct nouveau_oclass base;
11int nv04_devinit_fini(struct nouveau_object *, bool); 11 void (*meminit)(struct nouveau_devinit *);
12int nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32); 12 int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq);
13
14void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
15void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
16void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
17
18
19struct nv50_devinit_priv {
20 struct nouveau_devinit base;
21}; 13};
22 14
23int nv50_devinit_init(struct nouveau_object *); 15#define nouveau_devinit_create(p,e,o,d) \
16 nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d)
17#define nouveau_devinit_destroy(p) \
18 nouveau_subdev_destroy(&(p)->base)
19#define nouveau_devinit_init(p) ({ \
20 struct nouveau_devinit *d = (p); \
21 _nouveau_devinit_init(nv_object(d)); \
22})
23#define nouveau_devinit_fini(p,s) ({ \
24 struct nouveau_devinit *d = (p); \
25 _nouveau_devinit_fini(nv_object(d), (s)); \
26})
27
28int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *,
29 struct nouveau_oclass *, int, void **);
30#define _nouveau_devinit_dtor _nouveau_subdev_dtor
31int _nouveau_devinit_init(struct nouveau_object *);
32int _nouveau_devinit_fini(struct nouveau_object *, bool suspend);
24 33
25#endif 34#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-05 11:23:47 -0400