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authorThara Gopinath <thara@ti.com>2011-02-23 02:14:05 -0500
committerPaul Walmsley <paul@pwsan.com>2011-02-27 21:11:40 -0500
commitce722d269ff85ab11aa680784bcc6eff06e3e3ea (patch)
tree4db26e1d325609495b2dd74df48e751cd34ed00b
parentb6b582291fbe8cca987c8823c87ee4a62b24f105 (diff)
OMAP3: hwmod data: add dmtimer
Add dmtimer data. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c649
1 files changed, 649 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index e9d001228568..b8776ee241fa 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -24,6 +24,7 @@
24#include <plat/gpio.h> 24#include <plat/gpio.h>
25#include <plat/smartreflex.h> 25#include <plat/smartreflex.h>
26#include <plat/mcspi.h> 26#include <plat/mcspi.h>
27#include <plat/dmtimer.h>
27 28
28#include "omap_hwmod_common_data.h" 29#include "omap_hwmod_common_data.h"
29 30
@@ -515,6 +516,640 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
515 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 516 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
516}; 517};
517 518
519/* timer class */
520static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
521 .rev_offs = 0x0000,
522 .sysc_offs = 0x0010,
523 .syss_offs = 0x0014,
524 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
525 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
526 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
527 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
528 .sysc_fields = &omap_hwmod_sysc_type1,
529};
530
531static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
532 .name = "timer",
533 .sysc = &omap3xxx_timer_1ms_sysc,
534 .rev = OMAP_TIMER_IP_VERSION_1,
535};
536
537static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
538 .rev_offs = 0x0000,
539 .sysc_offs = 0x0010,
540 .syss_offs = 0x0014,
541 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
542 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
543 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
544 .sysc_fields = &omap_hwmod_sysc_type1,
545};
546
547static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
548 .name = "timer",
549 .sysc = &omap3xxx_timer_sysc,
550 .rev = OMAP_TIMER_IP_VERSION_1,
551};
552
553/* timer1 */
554static struct omap_hwmod omap3xxx_timer1_hwmod;
555static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
556 { .irq = 37, },
557};
558
559static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
560 {
561 .pa_start = 0x48318000,
562 .pa_end = 0x48318000 + SZ_1K - 1,
563 .flags = ADDR_TYPE_RT
564 },
565};
566
567/* l4_wkup -> timer1 */
568static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
569 .master = &omap3xxx_l4_wkup_hwmod,
570 .slave = &omap3xxx_timer1_hwmod,
571 .clk = "gpt1_ick",
572 .addr = omap3xxx_timer1_addrs,
573 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
574 .user = OCP_USER_MPU | OCP_USER_SDMA,
575};
576
577/* timer1 slave port */
578static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
579 &omap3xxx_l4_wkup__timer1,
580};
581
582/* timer1 hwmod */
583static struct omap_hwmod omap3xxx_timer1_hwmod = {
584 .name = "timer1",
585 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
586 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
587 .main_clk = "gpt1_fck",
588 .prcm = {
589 .omap2 = {
590 .prcm_reg_id = 1,
591 .module_bit = OMAP3430_EN_GPT1_SHIFT,
592 .module_offs = WKUP_MOD,
593 .idlest_reg_id = 1,
594 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
595 },
596 },
597 .slaves = omap3xxx_timer1_slaves,
598 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
599 .class = &omap3xxx_timer_1ms_hwmod_class,
600 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
601};
602
603/* timer2 */
604static struct omap_hwmod omap3xxx_timer2_hwmod;
605static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
606 { .irq = 38, },
607};
608
609static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
610 {
611 .pa_start = 0x49032000,
612 .pa_end = 0x49032000 + SZ_1K - 1,
613 .flags = ADDR_TYPE_RT
614 },
615};
616
617/* l4_per -> timer2 */
618static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
619 .master = &omap3xxx_l4_per_hwmod,
620 .slave = &omap3xxx_timer2_hwmod,
621 .clk = "gpt2_ick",
622 .addr = omap3xxx_timer2_addrs,
623 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
625};
626
627/* timer2 slave port */
628static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
629 &omap3xxx_l4_per__timer2,
630};
631
632/* timer2 hwmod */
633static struct omap_hwmod omap3xxx_timer2_hwmod = {
634 .name = "timer2",
635 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
636 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
637 .main_clk = "gpt2_fck",
638 .prcm = {
639 .omap2 = {
640 .prcm_reg_id = 1,
641 .module_bit = OMAP3430_EN_GPT2_SHIFT,
642 .module_offs = OMAP3430_PER_MOD,
643 .idlest_reg_id = 1,
644 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
645 },
646 },
647 .slaves = omap3xxx_timer2_slaves,
648 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
649 .class = &omap3xxx_timer_1ms_hwmod_class,
650 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
651};
652
653/* timer3 */
654static struct omap_hwmod omap3xxx_timer3_hwmod;
655static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
656 { .irq = 39, },
657};
658
659static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
660 {
661 .pa_start = 0x49034000,
662 .pa_end = 0x49034000 + SZ_1K - 1,
663 .flags = ADDR_TYPE_RT
664 },
665};
666
667/* l4_per -> timer3 */
668static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
669 .master = &omap3xxx_l4_per_hwmod,
670 .slave = &omap3xxx_timer3_hwmod,
671 .clk = "gpt3_ick",
672 .addr = omap3xxx_timer3_addrs,
673 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
674 .user = OCP_USER_MPU | OCP_USER_SDMA,
675};
676
677/* timer3 slave port */
678static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
679 &omap3xxx_l4_per__timer3,
680};
681
682/* timer3 hwmod */
683static struct omap_hwmod omap3xxx_timer3_hwmod = {
684 .name = "timer3",
685 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
686 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
687 .main_clk = "gpt3_fck",
688 .prcm = {
689 .omap2 = {
690 .prcm_reg_id = 1,
691 .module_bit = OMAP3430_EN_GPT3_SHIFT,
692 .module_offs = OMAP3430_PER_MOD,
693 .idlest_reg_id = 1,
694 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
695 },
696 },
697 .slaves = omap3xxx_timer3_slaves,
698 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
699 .class = &omap3xxx_timer_hwmod_class,
700 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
701};
702
703/* timer4 */
704static struct omap_hwmod omap3xxx_timer4_hwmod;
705static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
706 { .irq = 40, },
707};
708
709static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
710 {
711 .pa_start = 0x49036000,
712 .pa_end = 0x49036000 + SZ_1K - 1,
713 .flags = ADDR_TYPE_RT
714 },
715};
716
717/* l4_per -> timer4 */
718static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
719 .master = &omap3xxx_l4_per_hwmod,
720 .slave = &omap3xxx_timer4_hwmod,
721 .clk = "gpt4_ick",
722 .addr = omap3xxx_timer4_addrs,
723 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
724 .user = OCP_USER_MPU | OCP_USER_SDMA,
725};
726
727/* timer4 slave port */
728static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
729 &omap3xxx_l4_per__timer4,
730};
731
732/* timer4 hwmod */
733static struct omap_hwmod omap3xxx_timer4_hwmod = {
734 .name = "timer4",
735 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
736 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
737 .main_clk = "gpt4_fck",
738 .prcm = {
739 .omap2 = {
740 .prcm_reg_id = 1,
741 .module_bit = OMAP3430_EN_GPT4_SHIFT,
742 .module_offs = OMAP3430_PER_MOD,
743 .idlest_reg_id = 1,
744 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
745 },
746 },
747 .slaves = omap3xxx_timer4_slaves,
748 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
749 .class = &omap3xxx_timer_hwmod_class,
750 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
751};
752
753/* timer5 */
754static struct omap_hwmod omap3xxx_timer5_hwmod;
755static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
756 { .irq = 41, },
757};
758
759static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
760 {
761 .pa_start = 0x49038000,
762 .pa_end = 0x49038000 + SZ_1K - 1,
763 .flags = ADDR_TYPE_RT
764 },
765};
766
767/* l4_per -> timer5 */
768static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
769 .master = &omap3xxx_l4_per_hwmod,
770 .slave = &omap3xxx_timer5_hwmod,
771 .clk = "gpt5_ick",
772 .addr = omap3xxx_timer5_addrs,
773 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
774 .user = OCP_USER_MPU | OCP_USER_SDMA,
775};
776
777/* timer5 slave port */
778static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
779 &omap3xxx_l4_per__timer5,
780};
781
782/* timer5 hwmod */
783static struct omap_hwmod omap3xxx_timer5_hwmod = {
784 .name = "timer5",
785 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
786 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
787 .main_clk = "gpt5_fck",
788 .prcm = {
789 .omap2 = {
790 .prcm_reg_id = 1,
791 .module_bit = OMAP3430_EN_GPT5_SHIFT,
792 .module_offs = OMAP3430_PER_MOD,
793 .idlest_reg_id = 1,
794 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
795 },
796 },
797 .slaves = omap3xxx_timer5_slaves,
798 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
799 .class = &omap3xxx_timer_hwmod_class,
800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
801};
802
803/* timer6 */
804static struct omap_hwmod omap3xxx_timer6_hwmod;
805static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
806 { .irq = 42, },
807};
808
809static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
810 {
811 .pa_start = 0x4903A000,
812 .pa_end = 0x4903A000 + SZ_1K - 1,
813 .flags = ADDR_TYPE_RT
814 },
815};
816
817/* l4_per -> timer6 */
818static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
819 .master = &omap3xxx_l4_per_hwmod,
820 .slave = &omap3xxx_timer6_hwmod,
821 .clk = "gpt6_ick",
822 .addr = omap3xxx_timer6_addrs,
823 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
825};
826
827/* timer6 slave port */
828static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
829 &omap3xxx_l4_per__timer6,
830};
831
832/* timer6 hwmod */
833static struct omap_hwmod omap3xxx_timer6_hwmod = {
834 .name = "timer6",
835 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
836 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
837 .main_clk = "gpt6_fck",
838 .prcm = {
839 .omap2 = {
840 .prcm_reg_id = 1,
841 .module_bit = OMAP3430_EN_GPT6_SHIFT,
842 .module_offs = OMAP3430_PER_MOD,
843 .idlest_reg_id = 1,
844 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
845 },
846 },
847 .slaves = omap3xxx_timer6_slaves,
848 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
849 .class = &omap3xxx_timer_hwmod_class,
850 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
851};
852
853/* timer7 */
854static struct omap_hwmod omap3xxx_timer7_hwmod;
855static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
856 { .irq = 43, },
857};
858
859static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
860 {
861 .pa_start = 0x4903C000,
862 .pa_end = 0x4903C000 + SZ_1K - 1,
863 .flags = ADDR_TYPE_RT
864 },
865};
866
867/* l4_per -> timer7 */
868static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
869 .master = &omap3xxx_l4_per_hwmod,
870 .slave = &omap3xxx_timer7_hwmod,
871 .clk = "gpt7_ick",
872 .addr = omap3xxx_timer7_addrs,
873 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
874 .user = OCP_USER_MPU | OCP_USER_SDMA,
875};
876
877/* timer7 slave port */
878static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
879 &omap3xxx_l4_per__timer7,
880};
881
882/* timer7 hwmod */
883static struct omap_hwmod omap3xxx_timer7_hwmod = {
884 .name = "timer7",
885 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
886 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
887 .main_clk = "gpt7_fck",
888 .prcm = {
889 .omap2 = {
890 .prcm_reg_id = 1,
891 .module_bit = OMAP3430_EN_GPT7_SHIFT,
892 .module_offs = OMAP3430_PER_MOD,
893 .idlest_reg_id = 1,
894 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
895 },
896 },
897 .slaves = omap3xxx_timer7_slaves,
898 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
899 .class = &omap3xxx_timer_hwmod_class,
900 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
901};
902
903/* timer8 */
904static struct omap_hwmod omap3xxx_timer8_hwmod;
905static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
906 { .irq = 44, },
907};
908
909static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
910 {
911 .pa_start = 0x4903E000,
912 .pa_end = 0x4903E000 + SZ_1K - 1,
913 .flags = ADDR_TYPE_RT
914 },
915};
916
917/* l4_per -> timer8 */
918static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
919 .master = &omap3xxx_l4_per_hwmod,
920 .slave = &omap3xxx_timer8_hwmod,
921 .clk = "gpt8_ick",
922 .addr = omap3xxx_timer8_addrs,
923 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
924 .user = OCP_USER_MPU | OCP_USER_SDMA,
925};
926
927/* timer8 slave port */
928static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
929 &omap3xxx_l4_per__timer8,
930};
931
932/* timer8 hwmod */
933static struct omap_hwmod omap3xxx_timer8_hwmod = {
934 .name = "timer8",
935 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
936 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
937 .main_clk = "gpt8_fck",
938 .prcm = {
939 .omap2 = {
940 .prcm_reg_id = 1,
941 .module_bit = OMAP3430_EN_GPT8_SHIFT,
942 .module_offs = OMAP3430_PER_MOD,
943 .idlest_reg_id = 1,
944 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
945 },
946 },
947 .slaves = omap3xxx_timer8_slaves,
948 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
949 .class = &omap3xxx_timer_hwmod_class,
950 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
951};
952
953/* timer9 */
954static struct omap_hwmod omap3xxx_timer9_hwmod;
955static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
956 { .irq = 45, },
957};
958
959static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
960 {
961 .pa_start = 0x49040000,
962 .pa_end = 0x49040000 + SZ_1K - 1,
963 .flags = ADDR_TYPE_RT
964 },
965};
966
967/* l4_per -> timer9 */
968static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
969 .master = &omap3xxx_l4_per_hwmod,
970 .slave = &omap3xxx_timer9_hwmod,
971 .clk = "gpt9_ick",
972 .addr = omap3xxx_timer9_addrs,
973 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
974 .user = OCP_USER_MPU | OCP_USER_SDMA,
975};
976
977/* timer9 slave port */
978static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
979 &omap3xxx_l4_per__timer9,
980};
981
982/* timer9 hwmod */
983static struct omap_hwmod omap3xxx_timer9_hwmod = {
984 .name = "timer9",
985 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
986 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
987 .main_clk = "gpt9_fck",
988 .prcm = {
989 .omap2 = {
990 .prcm_reg_id = 1,
991 .module_bit = OMAP3430_EN_GPT9_SHIFT,
992 .module_offs = OMAP3430_PER_MOD,
993 .idlest_reg_id = 1,
994 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
995 },
996 },
997 .slaves = omap3xxx_timer9_slaves,
998 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
999 .class = &omap3xxx_timer_hwmod_class,
1000 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1001};
1002
1003/* timer10 */
1004static struct omap_hwmod omap3xxx_timer10_hwmod;
1005static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1006 { .irq = 46, },
1007};
1008
1009static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1010 {
1011 .pa_start = 0x48086000,
1012 .pa_end = 0x48086000 + SZ_1K - 1,
1013 .flags = ADDR_TYPE_RT
1014 },
1015};
1016
1017/* l4_core -> timer10 */
1018static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1019 .master = &omap3xxx_l4_core_hwmod,
1020 .slave = &omap3xxx_timer10_hwmod,
1021 .clk = "gpt10_ick",
1022 .addr = omap3xxx_timer10_addrs,
1023 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1024 .user = OCP_USER_MPU | OCP_USER_SDMA,
1025};
1026
1027/* timer10 slave port */
1028static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1029 &omap3xxx_l4_core__timer10,
1030};
1031
1032/* timer10 hwmod */
1033static struct omap_hwmod omap3xxx_timer10_hwmod = {
1034 .name = "timer10",
1035 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1036 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1037 .main_clk = "gpt10_fck",
1038 .prcm = {
1039 .omap2 = {
1040 .prcm_reg_id = 1,
1041 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1042 .module_offs = CORE_MOD,
1043 .idlest_reg_id = 1,
1044 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1045 },
1046 },
1047 .slaves = omap3xxx_timer10_slaves,
1048 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1049 .class = &omap3xxx_timer_1ms_hwmod_class,
1050 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1051};
1052
1053/* timer11 */
1054static struct omap_hwmod omap3xxx_timer11_hwmod;
1055static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1056 { .irq = 47, },
1057};
1058
1059static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1060 {
1061 .pa_start = 0x48088000,
1062 .pa_end = 0x48088000 + SZ_1K - 1,
1063 .flags = ADDR_TYPE_RT
1064 },
1065};
1066
1067/* l4_core -> timer11 */
1068static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1069 .master = &omap3xxx_l4_core_hwmod,
1070 .slave = &omap3xxx_timer11_hwmod,
1071 .clk = "gpt11_ick",
1072 .addr = omap3xxx_timer11_addrs,
1073 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1074 .user = OCP_USER_MPU | OCP_USER_SDMA,
1075};
1076
1077/* timer11 slave port */
1078static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1079 &omap3xxx_l4_core__timer11,
1080};
1081
1082/* timer11 hwmod */
1083static struct omap_hwmod omap3xxx_timer11_hwmod = {
1084 .name = "timer11",
1085 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1086 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1087 .main_clk = "gpt11_fck",
1088 .prcm = {
1089 .omap2 = {
1090 .prcm_reg_id = 1,
1091 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1092 .module_offs = CORE_MOD,
1093 .idlest_reg_id = 1,
1094 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1095 },
1096 },
1097 .slaves = omap3xxx_timer11_slaves,
1098 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1099 .class = &omap3xxx_timer_hwmod_class,
1100 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1101};
1102
1103/* timer12*/
1104static struct omap_hwmod omap3xxx_timer12_hwmod;
1105static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1106 { .irq = 95, },
1107};
1108
1109static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1110 {
1111 .pa_start = 0x48304000,
1112 .pa_end = 0x48304000 + SZ_1K - 1,
1113 .flags = ADDR_TYPE_RT
1114 },
1115};
1116
1117/* l4_core -> timer12 */
1118static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1119 .master = &omap3xxx_l4_core_hwmod,
1120 .slave = &omap3xxx_timer12_hwmod,
1121 .clk = "gpt12_ick",
1122 .addr = omap3xxx_timer12_addrs,
1123 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1124 .user = OCP_USER_MPU | OCP_USER_SDMA,
1125};
1126
1127/* timer12 slave port */
1128static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1129 &omap3xxx_l4_core__timer12,
1130};
1131
1132/* timer12 hwmod */
1133static struct omap_hwmod omap3xxx_timer12_hwmod = {
1134 .name = "timer12",
1135 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1136 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1137 .main_clk = "gpt12_fck",
1138 .prcm = {
1139 .omap2 = {
1140 .prcm_reg_id = 1,
1141 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1142 .module_offs = WKUP_MOD,
1143 .idlest_reg_id = 1,
1144 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1145 },
1146 },
1147 .slaves = omap3xxx_timer12_slaves,
1148 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1149 .class = &omap3xxx_timer_hwmod_class,
1150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1151};
1152
518/* l4_wkup -> wd_timer2 */ 1153/* l4_wkup -> wd_timer2 */
519static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { 1154static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
520 { 1155 {
@@ -2219,6 +2854,20 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2219 &omap3xxx_l4_wkup_hwmod, 2854 &omap3xxx_l4_wkup_hwmod,
2220 &omap3xxx_mpu_hwmod, 2855 &omap3xxx_mpu_hwmod,
2221 &omap3xxx_iva_hwmod, 2856 &omap3xxx_iva_hwmod,
2857
2858 &omap3xxx_timer1_hwmod,
2859 &omap3xxx_timer2_hwmod,
2860 &omap3xxx_timer3_hwmod,
2861 &omap3xxx_timer4_hwmod,
2862 &omap3xxx_timer5_hwmod,
2863 &omap3xxx_timer6_hwmod,
2864 &omap3xxx_timer7_hwmod,
2865 &omap3xxx_timer8_hwmod,
2866 &omap3xxx_timer9_hwmod,
2867 &omap3xxx_timer10_hwmod,
2868 &omap3xxx_timer11_hwmod,
2869 &omap3xxx_timer12_hwmod,
2870
2222 &omap3xxx_wd_timer2_hwmod, 2871 &omap3xxx_wd_timer2_hwmod,
2223 &omap3xxx_uart1_hwmod, 2872 &omap3xxx_uart1_hwmod,
2224 &omap3xxx_uart2_hwmod, 2873 &omap3xxx_uart2_hwmod,
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-05 08:51:19 -0500