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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-03-16 08:01:28 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-03-16 11:58:08 -0400
commitcdce4e9ba7ff86a5f43b971a9af88b25a3f6c9a4 (patch)
treef8993127b71fbdb23f092dcc54cb7021c0e49e47
parent7245387e36e16ae918467685c34510606fd74b7c (diff)
ASoC: Allow configuration of WM8904 GPIO pin functions
Provide platform data allowing the configuration of the GPIO pins on the WM8904 to be selected, allowing alternate functions to be enabled. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat
-rw-r--r--include/sound/wm8904.h74
-rw-r--r--sound/soc/codecs/wm8904.c12
-rw-r--r--sound/soc/codecs/wm8904.h64
3 files changed, 84 insertions, 66 deletions
diff --git a/include/sound/wm8904.h b/include/sound/wm8904.h
index d66575a601be..ddeeebf7c426 100644
--- a/include/sound/wm8904.h
+++ b/include/sound/wm8904.h
@@ -15,8 +15,76 @@
15#ifndef __MFD_WM8994_PDATA_H__ 15#ifndef __MFD_WM8994_PDATA_H__
16#define __MFD_WM8994_PDATA_H__ 16#define __MFD_WM8994_PDATA_H__
17 17
18#define WM8904_DRC_REGS 4 18/* Used to enable configuration of a GPIO to all zeros */
19#define WM8904_EQ_REGS 25 19#define WM8904_GPIO_NO_CONFIG 0x8000
20
21/*
22 * R121 (0x79) - GPIO Control 1
23 */
24#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
25#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
26#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
27#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
28#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
29#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
30#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
31#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
32#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
33#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
34#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
35
36/*
37 * R122 (0x7A) - GPIO Control 2
38 */
39#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
40#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
41#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
42#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
43#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
44#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
45#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
46#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
47#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
48#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
49#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
50
51/*
52 * R123 (0x7B) - GPIO Control 3
53 */
54#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
55#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
56#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
57#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
58#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
59#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
60#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
61#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
62#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
63#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
64#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
65
66/*
67 * R124 (0x7C) - GPIO Control 4
68 */
69#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
70#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
71#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
72#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
73#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
74#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
75#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
76#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
77#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
78#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
79#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
80#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
81#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
82#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
83#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
84
85#define WM8904_GPIO_REGS 4
86#define WM8904_DRC_REGS 4
87#define WM8904_EQ_REGS 25
20 88
21/** 89/**
22 * DRC configurations are specified with a label and a set of register 90 * DRC configurations are specified with a label and a set of register
@@ -52,6 +120,8 @@ struct wm8904_pdata {
52 120
53 int num_retune_mobile_cfgs; 121 int num_retune_mobile_cfgs;
54 struct wm8904_retune_mobile_cfg *retune_mobile_cfgs; 122 struct wm8904_retune_mobile_cfg *retune_mobile_cfgs;
123
124 u32 gpio_cfg[WM8904_GPIO_REGS];
55}; 125};
56 126
57#endif 127#endif
diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
index 593e47d0e0eb..ce3f004217ae 100644
--- a/sound/soc/codecs/wm8904.c
+++ b/sound/soc/codecs/wm8904.c
@@ -2425,6 +2425,7 @@ EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904);
2425static int wm8904_register(struct wm8904_priv *wm8904, 2425static int wm8904_register(struct wm8904_priv *wm8904,
2426 enum snd_soc_control_type control) 2426 enum snd_soc_control_type control)
2427{ 2427{
2428 struct wm8904_pdata *pdata = wm8904->pdata;
2428 int ret; 2429 int ret;
2429 struct snd_soc_codec *codec = &wm8904->codec; 2430 struct snd_soc_codec *codec = &wm8904->codec;
2430 int i; 2431 int i;
@@ -2530,6 +2531,17 @@ static int wm8904_register(struct wm8904_priv *wm8904,
2530 WM8904_LINEOUTRZC; 2531 WM8904_LINEOUTRZC;
2531 wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; 2532 wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
2532 2533
2534 /* Apply configuration from the platform data. */
2535 if (wm8904->pdata) {
2536 for (i = 0; i < WM8904_GPIO_REGS; i++) {
2537 if (!pdata->gpio_cfg[i])
2538 continue;
2539
2540 wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i]
2541 = pdata->gpio_cfg[i] & 0xffff;
2542 }
2543 }
2544
2533 /* Set Class W by default - this will be managed by the Class 2545 /* Set Class W by default - this will be managed by the Class
2534 * G widget at runtime where bypass paths are available. 2546 * G widget at runtime where bypass paths are available.
2535 */ 2547 */
diff --git a/sound/soc/codecs/wm8904.h b/sound/soc/codecs/wm8904.h
index b68886df34e4..10603a75c1a5 100644
--- a/sound/soc/codecs/wm8904.h
+++ b/sound/soc/codecs/wm8904.h
@@ -1200,70 +1200,6 @@ extern struct snd_soc_codec_device soc_codec_dev_wm8904;
1200#define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */ 1200#define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
1201 1201
1202/* 1202/*
1203 * R121 (0x79) - GPIO Control 1
1204 */
1205#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
1206#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
1207#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
1208#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
1209#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
1210#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
1211#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
1212#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
1213#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
1214#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
1215#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
1216
1217/*
1218 * R122 (0x7A) - GPIO Control 2
1219 */
1220#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
1221#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
1222#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
1223#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
1224#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
1225#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
1226#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
1227#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
1228#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
1229#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
1230#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
1231
1232/*
1233 * R123 (0x7B) - GPIO Control 3
1234 */
1235#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
1236#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
1237#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
1238#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
1239#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
1240#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
1241#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
1242#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
1243#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
1244#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
1245#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
1246
1247/*
1248 * R124 (0x7C) - GPIO Control 4
1249 */
1250#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
1251#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
1252#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
1253#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
1254#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
1255#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
1256#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
1257#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
1258#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
1259#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
1260#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
1261#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
1262#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
1263#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
1264#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
1265
1266/*
1267 * R126 (0x7E) - Digital Pulls 1203 * R126 (0x7E) - Digital Pulls
1268 */ 1204 */
1269#define WM8904_MCLK_PU 0x0080 /* MCLK_PU */ 1205#define WM8904_MCLK_PU 0x0080 /* MCLK_PU */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-03 08:26:01 -0400