diff options
| author | Andi Kleen <ak@linux.intel.com> | 2015-03-20 13:11:24 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-04-02 11:33:20 -0400 |
| commit | cd1f11de69226cc7ce7e7f22bdab9010103ddaa6 (patch) | |
| tree | 6543b48a8b40ab87617790a9a40a5cc52ea1828b | |
| parent | 1a78d93750bb5f61abdc59a91fc3bd06a214542a (diff) | |
perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs
perf with LBRs on has a tendency to rewrite the DEBUGCTL MSR with
the same value. Add a little optimization to skip the unnecessary
write.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1426871484-21285-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel_lbr.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c index 3d537252f011..94e5b506caa6 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c | |||
| @@ -135,7 +135,7 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); | |||
| 135 | static void __intel_pmu_lbr_enable(bool pmi) | 135 | static void __intel_pmu_lbr_enable(bool pmi) |
| 136 | { | 136 | { |
| 137 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | 137 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
| 138 | u64 debugctl, lbr_select = 0; | 138 | u64 debugctl, lbr_select = 0, orig_debugctl; |
| 139 | 139 | ||
| 140 | /* | 140 | /* |
| 141 | * No need to reprogram LBR_SELECT in a PMI, as it | 141 | * No need to reprogram LBR_SELECT in a PMI, as it |
| @@ -147,6 +147,7 @@ static void __intel_pmu_lbr_enable(bool pmi) | |||
| 147 | } | 147 | } |
| 148 | 148 | ||
| 149 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | 149 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
| 150 | orig_debugctl = debugctl; | ||
| 150 | debugctl |= DEBUGCTLMSR_LBR; | 151 | debugctl |= DEBUGCTLMSR_LBR; |
| 151 | /* | 152 | /* |
| 152 | * LBR callstack does not work well with FREEZE_LBRS_ON_PMI. | 153 | * LBR callstack does not work well with FREEZE_LBRS_ON_PMI. |
| @@ -155,7 +156,8 @@ static void __intel_pmu_lbr_enable(bool pmi) | |||
| 155 | */ | 156 | */ |
| 156 | if (!(lbr_select & LBR_CALL_STACK)) | 157 | if (!(lbr_select & LBR_CALL_STACK)) |
| 157 | debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; | 158 | debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; |
| 158 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | 159 | if (orig_debugctl != debugctl) |
| 160 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | ||
| 159 | } | 161 | } |
| 160 | 162 | ||
| 161 | static void __intel_pmu_lbr_disable(void) | 163 | static void __intel_pmu_lbr_disable(void) |