drm/i915: add SSC offsets for SBI access

Different registers are identified by their target id and offset. To
simplify their programming, they are called as <RegisterName><TargetId>.
For example, SSCCTL register accessed through SBI at target id 6 and
offset 0c is called SBI_SSCCTL6.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0cf2bf8da996..5fe8e2dbef2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4129,6 +4129,21 @@
 #define  SBI_BUSY                               (0x1<<0)
 #define  SBI_READY                              (0x0<<0)
 
+/* SBI offsets */
+#define  SBI_SSCDIVINTPHASE6            0x0600
+#define   SBI_SSCDIVINTPHASE_DIVSEL_MASK        ((0x7f)<<1)
+#define   SBI_SSCDIVINTPHASE_DIVSEL(x)          ((x)<<1)
+#define   SBI_SSCDIVINTPHASE_INCVAL_MASK        ((0x7f)<<8)
+#define   SBI_SSCDIVINTPHASE_INCVAL(x)          ((x)<<8)
+#define   SBI_SSCDIVINTPHASE_DIR(x)                     ((x)<<15)
+#define   SBI_SSCDIVINTPHASE_PROPAGATE          (1<<0)
+#define  SBI_SSCCTL                                     0x020c
+#define  SBI_SSCCTL6                            0x060C
+#define   SBI_SSCCTL_DISABLE            (1<<0)
+#define  SBI_SSCAUXDIV6                         0x0610
+#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)         ((x)<<4)
+#define  SBI_DBUFF0                                     0x2a00
+
 /* LPT PIXCLK_GATE */
 #define PIXCLK_GATE                             0xC6020
 #define  PIXCLK_GATE_UNGATE             1<<0