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authorLinus Walleij <linus.walleij@linaro.org>2011-09-08 04:04:51 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-09-08 05:03:56 -0400
commitcc890cd78acd7ab03442907d354b6af34e973cb3 (patch)
tree67cf73ea730969ffc26c3a5c55de8d96bb8b6299
parent526a0dc771a5cac3224e26abd1f018976b967516 (diff)
ARM: 7083/1: rewrite U300 GPIO to use gpiolib
This rewrites the U300 GPIO so as to use gpiolib and struct gpio_chip instead of just generic GPIO, hiding all the platform specifics and passing in GPIO chip variant as platform data at runtime instead of the compiletime kludges. As a result <mach/gpio.h> is now empty for U300 and using just defaults. Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Debian kernel maintainers <debian-kernel@lists.debian.org> Cc: Arnaud Patard <arnaud.patard@rtp-net.org> Reported-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-u300/Kconfig1
-rw-r--r--arch/arm/mach-u300/core.c31
-rw-r--r--arch/arm/mach-u300/include/mach/gpio-u300.h149
-rw-r--r--arch/arm/mach-u300/include/mach/gpio.h47
-rw-r--r--arch/arm/mach-u300/include/mach/irqs.h25
-rw-r--r--drivers/gpio/Kconfig9
-rw-r--r--drivers/gpio/gpio-u300.c1189
8 files changed, 783 insertions, 669 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2c71a8f3535a..05589e85c180 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -836,6 +836,7 @@ config ARCH_U300
836 select CLKDEV_LOOKUP 836 select CLKDEV_LOOKUP
837 select HAVE_MACH_CLKDEV 837 select HAVE_MACH_CLKDEV
838 select GENERIC_GPIO 838 select GENERIC_GPIO
839 select ARCH_REQUIRE_GPIOLIB
839 help 840 help
840 Support for ST-Ericsson U300 series mobile platforms. 841 Support for ST-Ericsson U300 series mobile platforms.
841 842
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 32a7b0f7e9f7..7b5c229dc7ea 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -6,6 +6,7 @@ comment "ST-Ericsson Mobile Platform Products"
6 6
7config MACH_U300 7config MACH_U300
8 bool "U300" 8 bool "U300"
9 select GPIO_U300
9 10
10comment "ST-Ericsson U300/U330/U335/U365 Feature Selections" 11comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
11 12
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 399c89f14dfb..fd435f44098b 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -37,6 +37,7 @@
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/syscon.h> 38#include <mach/syscon.h>
39#include <mach/dma_channels.h> 39#include <mach/dma_channels.h>
40#include <mach/gpio-u300.h>
40 41
41#include "clock.h" 42#include "clock.h"
42#include "mmc.h" 43#include "mmc.h"
@@ -239,7 +240,7 @@ static struct resource gpio_resources[] = {
239 .end = IRQ_U300_GPIO_PORT2, 240 .end = IRQ_U300_GPIO_PORT2,
240 .flags = IORESOURCE_IRQ, 241 .flags = IORESOURCE_IRQ,
241 }, 242 },
242#ifdef U300_COH901571_3 243#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
243 { 244 {
244 .name = "gpio3", 245 .name = "gpio3",
245 .start = IRQ_U300_GPIO_PORT3, 246 .start = IRQ_U300_GPIO_PORT3,
@@ -252,6 +253,7 @@ static struct resource gpio_resources[] = {
252 .end = IRQ_U300_GPIO_PORT4, 253 .end = IRQ_U300_GPIO_PORT4,
253 .flags = IORESOURCE_IRQ, 254 .flags = IORESOURCE_IRQ,
254 }, 255 },
256#endif
255#ifdef CONFIG_MACH_U300_BS335 257#ifdef CONFIG_MACH_U300_BS335
256 { 258 {
257 .name = "gpio5", 259 .name = "gpio5",
@@ -266,7 +268,6 @@ static struct resource gpio_resources[] = {
266 .flags = IORESOURCE_IRQ, 268 .flags = IORESOURCE_IRQ,
267 }, 269 },
268#endif /* CONFIG_MACH_U300_BS335 */ 270#endif /* CONFIG_MACH_U300_BS335 */
269#endif /* U300_COH901571_3 */
270}; 271};
271 272
272static struct resource keypad_resources[] = { 273static struct resource keypad_resources[] = {
@@ -1556,11 +1557,35 @@ static struct platform_device i2c1_device = {
1556 .resource = i2c1_resources, 1557 .resource = i2c1_resources,
1557}; 1558};
1558 1559
1560/*
1561 * The different variants have a few different versions of the
1562 * GPIO block, with different number of ports.
1563 */
1564static struct u300_gpio_platform u300_gpio_plat = {
1565#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
1566 .variant = U300_GPIO_COH901335,
1567 .ports = 3,
1568#endif
1569#ifdef CONFIG_MACH_U300_BS335
1570 .variant = U300_GPIO_COH901571_3_BS335,
1571 .ports = 7,
1572#endif
1573#ifdef CONFIG_MACH_U300_BS365
1574 .variant = U300_GPIO_COH901571_3_BS365,
1575 .ports = 5,
1576#endif
1577 .gpio_base = 0,
1578 .gpio_irq_base = IRQ_U300_GPIO_BASE,
1579};
1580
1559static struct platform_device gpio_device = { 1581static struct platform_device gpio_device = {
1560 .name = "u300-gpio", 1582 .name = "u300-gpio",
1561 .id = -1, 1583 .id = -1,
1562 .num_resources = ARRAY_SIZE(gpio_resources), 1584 .num_resources = ARRAY_SIZE(gpio_resources),
1563 .resource = gpio_resources, 1585 .resource = gpio_resources,
1586 .dev = {
1587 .platform_data = &u300_gpio_plat,
1588 },
1564}; 1589};
1565 1590
1566static struct platform_device keypad_device = { 1591static struct platform_device keypad_device = {
@@ -1666,7 +1691,7 @@ void __init u300_init_irq(void)
1666 BUG_ON(IS_ERR(clk)); 1691 BUG_ON(IS_ERR(clk));
1667 clk_enable(clk); 1692 clk_enable(clk);
1668 1693
1669 for (i = 0; i < NR_IRQS; i++) 1694 for (i = 0; i < U300_VIC_IRQS_END; i++)
1670 set_bit(i, (unsigned long *) &mask[0]); 1695 set_bit(i, (unsigned long *) &mask[0]);
1671 vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); 1696 vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1672 vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); 1697 vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h
index a6119062add9..0c2b2021951a 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/arch/arm/mach-u300/include/mach/gpio-u300.h
@@ -9,132 +9,6 @@
9#ifndef __MACH_U300_GPIO_U300_H 9#ifndef __MACH_U300_GPIO_U300_H
10#define __MACH_U300_GPIO_U300_H 10#define __MACH_U300_GPIO_U300_H
11 11
12#include <linux/kernel.h>
13#include <linux/io.h>
14#include <mach/hardware.h>
15#include <asm/irq.h>
16
17/* Switch type depending on platform/chip variant */
18#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
19#define U300_COH901335
20#endif
21#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
22#define U300_COH901571_3
23#endif
24
25/* Get base address for regs here */
26#include "u300-regs.h"
27/* IRQ numbers */
28#include "irqs.h"
29
30/*
31 * This is the GPIO block definitions. GPIO (General Purpose I/O) can be
32 * used for anything, and often is. The event/enable etc figures are for
33 * the lowermost pin (pin 0 on each port), shift this left to match your
34 * pin if you're gonna use these values.
35 */
36#ifdef U300_COH901335
37#define U300_GPIO_PORTX_SPACING (0x1C)
38/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
39#define U300_GPIO_PXPDIR (0x00)
40#define U300_GPIO_PXPDOR (0x00)
41/* Port X Pin Config Register 32bit (R/W) */
42#define U300_GPIO_PXPCR (0x04)
43#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
44#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
45#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
46#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
47#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
48#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
49#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
50/* Port X Interrupt Event Register 32bit (R/W) */
51#define U300_GPIO_PXIEV (0x08)
52#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
53#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
54/* Port X Interrupt Enable Register 32bit (R/W) */
55#define U300_GPIO_PXIEN (0x0C)
56#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
57#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
58/* Port X Interrupt Force Register 32bit (R/W) */
59#define U300_GPIO_PXIFR (0x10)
60#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
61#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
62/* Port X Interrupt Config Register 32bit (R/W) */
63#define U300_GPIO_PXICR (0x14)
64#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
65#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
66#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
67#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
68/* Port X Pull-up Enable Register 32bit (R/W) */
69#define U300_GPIO_PXPER (0x18)
70#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
71#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
72/* Control Register 32bit (R/W) */
73#define U300_GPIO_CR (0x54)
74#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
75/* three ports of 8 bits each = GPIO pins 0..23 */
76#define U300_GPIO_NUM_PORTS 3
77#define U300_GPIO_PINS_PER_PORT 8
78#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
79#endif
80
81#ifdef U300_COH901571_3
82/*
83 * Control Register 32bit (R/W)
84 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
85 * gives the number of GPIO pins.
86 * bit 8-2 (mask 0x000001FC) contains the core version ID.
87 */
88#define U300_GPIO_CR (0x00)
89#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
90#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
91#define U300_GPIO_PORTX_SPACING (0x30)
92/* Port X Pin Data INPUT Register 32bit (R/W) */
93#define U300_GPIO_PXPDIR (0x04)
94/* Port X Pin Data OUTPUT Register 32bit (R/W) */
95#define U300_GPIO_PXPDOR (0x08)
96/* Port X Pin Config Register 32bit (R/W) */
97#define U300_GPIO_PXPCR (0x0C)
98#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
99#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
100#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
101#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
102#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
103#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
104#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
105/* Port X Pull-up Enable Register 32bit (R/W) */
106#define U300_GPIO_PXPER (0x10)
107#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
108#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
109/* Port X Interrupt Event Register 32bit (R/W) */
110#define U300_GPIO_PXIEV (0x14)
111#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
112#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
113/* Port X Interrupt Enable Register 32bit (R/W) */
114#define U300_GPIO_PXIEN (0x18)
115#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
116#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
117/* Port X Interrupt Force Register 32bit (R/W) */
118#define U300_GPIO_PXIFR (0x1C)
119#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
120#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
121/* Port X Interrupt Config Register 32bit (R/W) */
122#define U300_GPIO_PXICR (0x20)
123#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
124#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
125#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
126#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
127#ifdef CONFIG_MACH_U300_BS335
128/* seven ports of 8 bits each = GPIO pins 0..55 */
129#define U300_GPIO_NUM_PORTS 7
130#else
131/* five ports of 8 bits each = GPIO pins 0..39 */
132#define U300_GPIO_NUM_PORTS 5
133#endif
134#define U300_GPIO_PINS_PER_PORT 8
135#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
136#endif
137
138/* 12/*
139 * Individual pin assignments for the B26/S26. Notice that the 13 * Individual pin assignments for the B26/S26. Notice that the
140 * actual usage of these pins depends on the PAD MUX settings, that 14 * actual usage of these pins depends on the PAD MUX settings, that
@@ -250,4 +124,27 @@
250 124
251#endif 125#endif
252 126
127/**
128 * enum u300_gpio_variant - the type of U300 GPIO employed
129 */
130enum u300_gpio_variant {
131 U300_GPIO_COH901335,
132 U300_GPIO_COH901571_3_BS335,
133 U300_GPIO_COH901571_3_BS365,
134};
135
136/**
137 * struct u300_gpio_platform - U300 GPIO platform data
138 * @variant: IP block variant
139 * @ports: number of GPIO block ports
140 * @gpio_base: first GPIO number for this block (use a free range)
141 * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
142 */
143struct u300_gpio_platform {
144 enum u300_gpio_variant variant;
145 u8 ports;
146 int gpio_base;
147 int gpio_irq_base;
148};
149
253#endif /* __MACH_U300_GPIO_U300_H */ 150#endif /* __MACH_U300_GPIO_U300_H */
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
index 430a0544baff..e69de29bb2d1 100644
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -1,47 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/gpio.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * GPIO block resgister definitions and inline macros for
9 * U300 GPIO COH 901 335 or COH 901 571/3
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12
13#ifndef __MACH_U300_GPIO_H
14#define __MACH_U300_GPIO_H
15
16#define __ARM_GPIOLIB_COMPLEX
17
18/* These can be found in arch/arm/mach-u300/gpio.c */
19extern int gpio_is_valid(int number);
20extern int gpio_request(unsigned gpio, const char *label);
21extern void gpio_free(unsigned gpio);
22extern int gpio_direction_input(unsigned gpio);
23extern int gpio_direction_output(unsigned gpio, int value);
24extern int gpio_register_callback(unsigned gpio,
25 int (*func)(void *arg),
26 void *);
27extern int gpio_unregister_callback(unsigned gpio);
28extern void enable_irq_on_gpio_pin(unsigned gpio, int edge);
29extern void disable_irq_on_gpio_pin(unsigned gpio);
30extern void gpio_pullup(unsigned gpio, int value);
31extern int gpio_get_value(unsigned gpio);
32extern void gpio_set_value(unsigned gpio, int value);
33
34#define gpio_get_value_cansleep gpio_get_value
35#define gpio_set_value_cansleep gpio_set_value
36
37/* translates a pin number to a port number */
38#define PIN_TO_PORT(val) (val >> 3)
39
40/* wrappers to sleep-enable the previous two functions */
41static inline unsigned gpio_to_irq(unsigned gpio)
42{
43 return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0;
44}
45#define gpio_to_irq gpio_to_irq
46
47#endif /* __MACH_U300_GPIO_H */
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index 09b1b28fa8fd..d270fea32926 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -72,7 +72,7 @@
72 72
73/* DB3150 and DB3200 have only 45 IRQs */ 73/* DB3150 and DB3200 have only 45 IRQs */
74#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) 74#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
75#define U300_NR_IRQS 45 75#define U300_VIC_IRQS_END 45
76#endif 76#endif
77 77
78/* The DB3350-specific interrupt lines */ 78/* The DB3350-specific interrupt lines */
@@ -88,7 +88,7 @@
88#define IRQ_U300_GPIO_PORT4 53 88#define IRQ_U300_GPIO_PORT4 53
89#define IRQ_U300_GPIO_PORT5 54 89#define IRQ_U300_GPIO_PORT5 54
90#define IRQ_U300_GPIO_PORT6 55 90#define IRQ_U300_GPIO_PORT6 55
91#define U300_NR_IRQS 56 91#define U300_VIC_IRQS_END 56
92#endif 92#endif
93 93
94/* The DB3210-specific interrupt lines */ 94/* The DB3210-specific interrupt lines */
@@ -106,16 +106,25 @@
106#define IRQ_U300_NFIF 45 106#define IRQ_U300_NFIF 45
107#define IRQ_U300_NFIF2 46 107#define IRQ_U300_NFIF2 46
108#define IRQ_U300_SYSCON_PLL_LOCK 47 108#define IRQ_U300_SYSCON_PLL_LOCK 47
109#define U300_NR_IRQS 48 109#define U300_VIC_IRQS_END 48
110#endif 110#endif
111 111
112#ifdef CONFIG_AB3550_CORE 112/* Maximum 8*7 GPIO lines */
113#define IRQ_AB3550_BASE (U300_NR_IRQS) 113#ifdef CONFIG_GPIO_U300
114#define IRQ_AB3550_END (IRQ_AB3550_BASE + 37) 114#define IRQ_U300_GPIO_BASE (U300_VIC_IRQS_END)
115#define IRQ_U300_GPIO_END (IRQ_U300_GPIO_BASE + 56)
116#else
117#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
118#endif
115 119
116#define NR_IRQS (IRQ_AB3550_END + 1) 120/* Optional AB3550 mixsig chip */
121#ifdef CONFIG_AB3550_CORE
122#define IRQ_AB3550_BASE (IRQ_U300_GPIO_END)
123#define IRQ_AB3550_END (IRQ_AB3550_BASE + 38)
117#else 124#else
118#define NR_IRQS U300_NR_IRQS 125#define IRQ_AB3550_END (IRQ_U300_GPIO_END)
119#endif 126#endif
120 127
128#define NR_IRQS (IRQ_AB3550_END)
129
121#endif 130#endif
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d539efd96d4b..4caa3d37bbde 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -178,6 +178,15 @@ config GPIO_SCH
178 The Intel Tunnel Creek processor has 5 GPIOs powered by the 178 The Intel Tunnel Creek processor has 5 GPIOs powered by the
179 core power rail and 9 from suspend power supply. 179 core power rail and 9 from suspend power supply.
180 180
181config GPIO_U300
182 bool "ST-Ericsson U300 COH 901 335/571 GPIO"
183 depends on GPIOLIB && ARCH_U300
184 help
185 Say yes here to support GPIO interface on ST-Ericsson U300.
186 The names of the two IP block variants supported are
187 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
188 ports of 8 GPIO pins each.
189
181config GPIO_VX855 190config GPIO_VX855
182 tristate "VIA VX855/VX875 GPIO" 191 tristate "VIA VX855/VX875 GPIO"
183 depends on MFD_SUPPORT && PCI 192 depends on MFD_SUPPORT && PCI
diff --git a/drivers/gpio/gpio-u300.c b/drivers/gpio/gpio-u300.c
index 92f2b8c06de1..4035778852b0 100644
--- a/drivers/gpio/gpio-u300.c
+++ b/drivers/gpio/gpio-u300.c
@@ -1,18 +1,17 @@
1/* 1/*
2 * U300 GPIO module. 2 * U300 GPIO module.
3 * 3 *
4 * Copyright (C) 2007-2009 ST-Ericsson AB 4 * Copyright (C) 2007-2011 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2 5 * License terms: GNU General Public License (GPL) version 2
6 * This can driver either of the two basic GPIO cores 6 * This can driver either of the two basic GPIO cores
7 * available in the U300 platforms: 7 * available in the U300 platforms:
8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0) 8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) 9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
10 * Notice that you also have inline macros in <asm-arch/gpio.h> 10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 * Author: Linus Walleij <linus.walleij@stericsson.com>
12 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
13 *
14 */ 12 */
15#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/irq.h>
16#include <linux/interrupt.h> 15#include <linux/interrupt.h>
17#include <linux/delay.h> 16#include <linux/delay.h>
18#include <linux/errno.h> 17#include <linux/errno.h>
@@ -21,678 +20,898 @@
21#include <linux/err.h> 20#include <linux/err.h>
22#include <linux/platform_device.h> 21#include <linux/platform_device.h>
23#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/list.h>
24#include <linux/slab.h>
24#include <mach/gpio-u300.h> 25#include <mach/gpio-u300.h>
25 26
26/* Reference to GPIO block clock */ 27/*
27static struct clk *clk; 28 * Bias modes for U300 GPIOs
29 *
30 * GPIO_U300_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us
31 * GPIO_U300_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state
32 * is not controlled by software
33 * GPIO_U300_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high
34 * impedance to VDD)
35 */
36#define GPIO_U300_CONFIG_BIAS_UNKNOWN 0x1000
37#define GPIO_U300_CONFIG_BIAS_FLOAT 0x1001
38#define GPIO_U300_CONFIG_BIAS_PULL_UP 0x1002
28 39
29/* Memory resource */ 40/*
30static struct resource *memres; 41 * Drive modes for U300 GPIOs (output)
31static void __iomem *virtbase; 42 *
32static struct device *gpiodev; 43 * GPIO_U300_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and
44 * low, this is the most typical case and is typically achieved with two
45 * active transistors on the output
46 * GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain
47 * (open collector) which means it is usually wired with other output
48 * ports which are then pulled up with an external resistor
49 * GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain
50 * (open emitter) which is the same as open drain mutatis mutandis but
51 * pulled to ground
52 */
53#define GPIO_U300_CONFIG_DRIVE_PUSH_PULL 0x2000
54#define GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN 0x2001
55#define GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE 0x2002
56
57/*
58 * Register definitions for COH 901 335 variant
59 */
60#define U300_335_PORT_STRIDE (0x1C)
61/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
62#define U300_335_PXPDIR (0x00)
63#define U300_335_PXPDOR (0x00)
64/* Port X Pin Config Register 32bit (R/W) */
65#define U300_335_PXPCR (0x04)
66/* This register layout is the same in both blocks */
67#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
68#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
69#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
70#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
71#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
72#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
73#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
74/* Port X Interrupt Event Register 32bit (R/W) */
75#define U300_335_PXIEV (0x08)
76/* Port X Interrupt Enable Register 32bit (R/W) */
77#define U300_335_PXIEN (0x0C)
78/* Port X Interrupt Force Register 32bit (R/W) */
79#define U300_335_PXIFR (0x10)
80/* Port X Interrupt Config Register 32bit (R/W) */
81#define U300_335_PXICR (0x14)
82/* This register layout is the same in both blocks */
83#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
84#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
85#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
86#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
87/* Port X Pull-up Enable Register 32bit (R/W) */
88#define U300_335_PXPER (0x18)
89/* This register layout is the same in both blocks */
90#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
91#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
92/* Control Register 32bit (R/W) */
93#define U300_335_CR (0x54)
94#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
95
96/*
97 * Register definitions for COH 901 571 / 3 variant
98 */
99#define U300_571_PORT_STRIDE (0x30)
100/*
101 * Control Register 32bit (R/W)
102 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
103 * gives the number of GPIO pins.
104 * bit 8-2 (mask 0x000001FC) contains the core version ID.
105 */
106#define U300_571_CR (0x00)
107#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
108#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
109/*
110 * These registers have the same layout and function as the corresponding
111 * COH 901 335 registers, just at different offset.
112 */
113#define U300_571_PXPDIR (0x04)
114#define U300_571_PXPDOR (0x08)
115#define U300_571_PXPCR (0x0C)
116#define U300_571_PXPER (0x10)
117#define U300_571_PXIEV (0x14)
118#define U300_571_PXIEN (0x18)
119#define U300_571_PXIFR (0x1C)
120#define U300_571_PXICR (0x20)
121
122/* 8 bits per port, no version has more than 7 ports */
123#define U300_GPIO_PINS_PER_PORT 8
124#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
125
126struct u300_gpio {
127 struct gpio_chip chip;
128 struct list_head port_list;
129 struct clk *clk;
130 struct resource *memres;
131 void __iomem *base;
132 struct device *dev;
133 int irq_base;
134 u32 stride;
135 /* Register offsets */
136 u32 pcr;
137 u32 dor;
138 u32 dir;
139 u32 per;
140 u32 icr;
141 u32 ien;
142 u32 iev;
143};
33 144
34struct u300_gpio_port { 145struct u300_gpio_port {
35 const char *name; 146 struct list_head node;
147 struct u300_gpio *gpio;
148 char name[8];
36 int irq; 149 int irq;
37 int number; 150 int number;
151 u8 toggle_edge_mode;
38}; 152};
39 153
154/*
155 * Macro to expand to read a specific register found in the "gpio"
156 * struct. It requires the struct u300_gpio *gpio variable to exist in
157 * its context. It calculates the port offset from the given pin
158 * offset, muliplies by the port stride and adds the register offset
159 * so it provides a pointer to the desired register.
160 */
161#define U300_PIN_REG(pin, reg) \
162 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
40 163
41static struct u300_gpio_port gpio_ports[] = { 164/*
42 { 165 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
43 .name = "gpio0", 166 * register.
44 .number = 0, 167 */
45 }, 168#define U300_PIN_BIT(pin) \
46 { 169 (1 << (pin & 0x07))
47 .name = "gpio1",
48 .number = 1,
49 },
50 {
51 .name = "gpio2",
52 .number = 2,
53 },
54#ifdef U300_COH901571_3
55 {
56 .name = "gpio3",
57 .number = 3,
58 },
59 {
60 .name = "gpio4",
61 .number = 4,
62 },
63#ifdef CONFIG_MACH_U300_BS335
64 {
65 .name = "gpio5",
66 .number = 5,
67 },
68 {
69 .name = "gpio6",
70 .number = 6,
71 },
72#endif
73#endif
74 170
171struct u300_gpio_confdata {
172 u16 bias_mode;
173 bool output;
174 int outval;
75}; 175};
76 176
177/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
178#define BS335_GPIO_NUM_PORTS 7
179/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
180#define BS365_GPIO_NUM_PORTS 5
77 181
78#ifdef U300_COH901571_3 182#define U300_FLOATING_INPUT { \
183 .bias_mode = GPIO_U300_CONFIG_BIAS_FLOAT, \
184 .output = false, \
185}
79 186
80/* Default input value */ 187#define U300_PULL_UP_INPUT { \
81#define DEFAULT_OUTPUT_LOW 0 188 .bias_mode = GPIO_U300_CONFIG_BIAS_PULL_UP, \
82#define DEFAULT_OUTPUT_HIGH 1 189 .output = false, \
190}
83 191
84/* GPIO Pull-Up status */ 192#define U300_OUTPUT_LOW { \
85#define DISABLE_PULL_UP 0 193 .output = true, \
86#define ENABLE_PULL_UP 1 194 .outval = 0, \
195}
87 196
88#define GPIO_NOT_USED 0 197#define U300_OUTPUT_HIGH { \
89#define GPIO_IN 1 198 .output = true, \
90#define GPIO_OUT 2 199 .outval = 1, \
200}
91 201
92struct u300_gpio_configuration_data {
93 unsigned char pin_usage;
94 unsigned char default_output_value;
95 unsigned char pull_up;
96};
97 202
98/* Initial configuration */ 203/* Initial configuration */
99const struct u300_gpio_configuration_data 204static const struct __initdata u300_gpio_confdata
100u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 205bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
101#ifdef CONFIG_MACH_U300_BS335
102 /* Port 0, pins 0-7 */ 206 /* Port 0, pins 0-7 */
103 { 207 {
104 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 208 U300_FLOATING_INPUT,
105 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 209 U300_OUTPUT_HIGH,
106 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 210 U300_FLOATING_INPUT,
107 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 211 U300_OUTPUT_LOW,
108 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 212 U300_OUTPUT_LOW,
109 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 213 U300_OUTPUT_LOW,
110 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 214 U300_OUTPUT_LOW,
111 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 215 U300_OUTPUT_LOW,
112 }, 216 },
113 /* Port 1, pins 0-7 */ 217 /* Port 1, pins 0-7 */
114 { 218 {
115 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 219 U300_OUTPUT_LOW,
116 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 220 U300_OUTPUT_LOW,
117 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 221 U300_OUTPUT_LOW,
118 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 222 U300_PULL_UP_INPUT,
119 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 223 U300_FLOATING_INPUT,
120 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 224 U300_OUTPUT_HIGH,
121 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 225 U300_OUTPUT_LOW,
122 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 226 U300_OUTPUT_LOW,
123 }, 227 },
124 /* Port 2, pins 0-7 */ 228 /* Port 2, pins 0-7 */
125 { 229 {
126 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 230 U300_FLOATING_INPUT,
127 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 231 U300_FLOATING_INPUT,
128 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 232 U300_FLOATING_INPUT,
129 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 233 U300_FLOATING_INPUT,
130 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 234 U300_OUTPUT_LOW,
131 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 235 U300_PULL_UP_INPUT,
132 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 236 U300_OUTPUT_LOW,
133 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 237 U300_PULL_UP_INPUT,
134 }, 238 },
135 /* Port 3, pins 0-7 */ 239 /* Port 3, pins 0-7 */
136 { 240 {
137 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 241 U300_PULL_UP_INPUT,
138 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 242 U300_OUTPUT_LOW,
139 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 243 U300_FLOATING_INPUT,
140 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 244 U300_FLOATING_INPUT,
141 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 245 U300_FLOATING_INPUT,
142 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 246 U300_FLOATING_INPUT,
143 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 247 U300_FLOATING_INPUT,
144 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 248 U300_FLOATING_INPUT,
145 }, 249 },
146 /* Port 4, pins 0-7 */ 250 /* Port 4, pins 0-7 */
147 { 251 {
148 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 252 U300_FLOATING_INPUT,
149 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 253 U300_FLOATING_INPUT,
150 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 254 U300_FLOATING_INPUT,
151 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 255 U300_FLOATING_INPUT,
152 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 256 U300_FLOATING_INPUT,
153 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 257 U300_FLOATING_INPUT,
154 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 258 U300_FLOATING_INPUT,
155 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 259 U300_FLOATING_INPUT,
156 }, 260 },
157 /* Port 5, pins 0-7 */ 261 /* Port 5, pins 0-7 */
158 { 262 {
159 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 263 U300_FLOATING_INPUT,
160 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 264 U300_FLOATING_INPUT,
161 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 265 U300_FLOATING_INPUT,
162 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 266 U300_FLOATING_INPUT,
163 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 267 U300_FLOATING_INPUT,
164 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 268 U300_FLOATING_INPUT,
165 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 269 U300_FLOATING_INPUT,
166 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 270 U300_FLOATING_INPUT,
167 }, 271 },
168 /* Port 6, pind 0-7 */ 272 /* Port 6, pind 0-7 */
169 { 273 {
170 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 274 U300_FLOATING_INPUT,
171 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 275 U300_FLOATING_INPUT,
172 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 276 U300_FLOATING_INPUT,
173 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 277 U300_FLOATING_INPUT,
174 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 278 U300_FLOATING_INPUT,
175 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 279 U300_FLOATING_INPUT,
176 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 280 U300_FLOATING_INPUT,
177 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 281 U300_FLOATING_INPUT,
178 } 282 }
179#endif 283};
180 284
181#ifdef CONFIG_MACH_U300_BS365 285static const struct __initdata u300_gpio_confdata
286bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
182 /* Port 0, pins 0-7 */ 287 /* Port 0, pins 0-7 */
183 { 288 {
184 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 289 U300_FLOATING_INPUT,
185 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 290 U300_OUTPUT_LOW,
186 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 291 U300_FLOATING_INPUT,
187 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 292 U300_OUTPUT_LOW,
188 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 293 U300_OUTPUT_LOW,
189 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 294 U300_OUTPUT_LOW,
190 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 295 U300_PULL_UP_INPUT,
191 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 296 U300_FLOATING_INPUT,
192 }, 297 },
193 /* Port 1, pins 0-7 */ 298 /* Port 1, pins 0-7 */
194 { 299 {
195 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 300 U300_OUTPUT_LOW,
196 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 301 U300_FLOATING_INPUT,
197 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 302 U300_OUTPUT_LOW,
198 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 303 U300_FLOATING_INPUT,
199 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 304 U300_FLOATING_INPUT,
200 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 305 U300_OUTPUT_HIGH,
201 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 306 U300_OUTPUT_LOW,
202 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 307 U300_OUTPUT_LOW,
203 }, 308 },
204 /* Port 2, pins 0-7 */ 309 /* Port 2, pins 0-7 */
205 { 310 {
206 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 311 U300_FLOATING_INPUT,
207 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 312 U300_PULL_UP_INPUT,
208 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 313 U300_OUTPUT_LOW,
209 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 314 U300_OUTPUT_LOW,
210 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 315 U300_PULL_UP_INPUT,
211 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 316 U300_PULL_UP_INPUT,
212 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 317 U300_PULL_UP_INPUT,
213 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 318 U300_PULL_UP_INPUT,
214 }, 319 },
215 /* Port 3, pins 0-7 */ 320 /* Port 3, pins 0-7 */
216 { 321 {
217 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 322 U300_PULL_UP_INPUT,
218 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 323 U300_PULL_UP_INPUT,
219 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 324 U300_PULL_UP_INPUT,
220 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 325 U300_PULL_UP_INPUT,
221 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 326 U300_PULL_UP_INPUT,
222 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 327 U300_PULL_UP_INPUT,
223 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 328 U300_PULL_UP_INPUT,
224 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 329 U300_PULL_UP_INPUT,
225 }, 330 },
226 /* Port 4, pins 0-7 */ 331 /* Port 4, pins 0-7 */
227 { 332 {
228 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 333 U300_PULL_UP_INPUT,
229 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 334 U300_PULL_UP_INPUT,
230 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 335 U300_PULL_UP_INPUT,
231 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 336 U300_PULL_UP_INPUT,
232 /* These 4 pins doesn't exist on DB3210 */ 337 /* These 4 pins doesn't exist on DB3210 */
233 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 338 U300_OUTPUT_LOW,
234 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 339 U300_OUTPUT_LOW,
235 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 340 U300_OUTPUT_LOW,
236 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 341 U300_OUTPUT_LOW,
237 } 342 }
238#endif
239}; 343};
240#endif
241 344
242 345/**
243/* No users == we can power down GPIO */ 346 * to_u300_gpio() - get the pointer to u300_gpio
244static int gpio_users; 347 * @chip: the gpio chip member of the structure u300_gpio
245
246struct gpio_struct {
247 int (*callback)(void *);
248 void *data;
249 int users;
250};
251
252static struct gpio_struct gpio_pin[U300_GPIO_MAX];
253
254/*
255 * Let drivers register callback in order to get notified when there is
256 * an interrupt on the gpio pin
257 */ 348 */
258int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data) 349static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
259{ 350{
260 if (gpio_pin[gpio].callback) 351 return container_of(chip, struct u300_gpio, chip);
261 dev_warn(gpiodev, "%s: WARNING: callback already "
262 "registered for gpio pin#%d\n", __func__, gpio);
263 gpio_pin[gpio].callback = func;
264 gpio_pin[gpio].data = data;
265
266 return 0;
267} 352}
268EXPORT_SYMBOL(gpio_register_callback);
269 353
270int gpio_unregister_callback(unsigned gpio) 354static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
271{ 355{
272 if (!gpio_pin[gpio].callback) 356 struct u300_gpio *gpio = to_u300_gpio(chip);
273 dev_warn(gpiodev, "%s: WARNING: callback already "
274 "unregistered for gpio pin#%d\n", __func__, gpio);
275 gpio_pin[gpio].callback = NULL;
276 gpio_pin[gpio].data = NULL;
277 357
278 return 0; 358 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
279} 359}
280EXPORT_SYMBOL(gpio_unregister_callback);
281 360
282/* Non-zero means valid */ 361static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
283int gpio_is_valid(int number)
284{ 362{
285 if (number >= 0 && 363 struct u300_gpio *gpio = to_u300_gpio(chip);
286 number < (U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT)) 364 unsigned long flags;
287 return 1; 365 u32 val;
288 return 0;
289}
290EXPORT_SYMBOL(gpio_is_valid);
291 366
292int gpio_request(unsigned gpio, const char *label) 367 local_irq_save(flags);
293{
294 if (gpio_pin[gpio].users)
295 return -EINVAL;
296 else
297 gpio_pin[gpio].users++;
298 368
299 gpio_users++; 369 val = readl(U300_PIN_REG(offset, dor));
370 if (value)
371 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
372 else
373 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
300 374
301 return 0; 375 local_irq_restore(flags);
302} 376}
303EXPORT_SYMBOL(gpio_request);
304 377
305void gpio_free(unsigned gpio) 378static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
306{ 379{
307 gpio_users--; 380 struct u300_gpio *gpio = to_u300_gpio(chip);
308 gpio_pin[gpio].users--; 381 unsigned long flags;
309 if (unlikely(gpio_pin[gpio].users < 0)) { 382 u32 val;
310 dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
311 gpio);
312 gpio_pin[gpio].users = 0;
313 }
314
315 return;
316}
317EXPORT_SYMBOL(gpio_free);
318 383
319/* This returns zero or nonzero */ 384 local_irq_save(flags);
320int gpio_get_value(unsigned gpio) 385 val = readl(U300_PIN_REG(offset, pcr));
321{ 386 /* Mask out this pin, note 2 bits per setting */
322 return readl(virtbase + U300_GPIO_PXPDIR + 387 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
323 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07)); 388 writel(val, U300_PIN_REG(offset, pcr));
389 local_irq_restore(flags);
390 return 0;
324} 391}
325EXPORT_SYMBOL(gpio_get_value);
326 392
327/* 393static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
328 * We hope that the compiler will optimize away the unused branch 394 int value)
329 * in case "value" is a constant
330 */
331void gpio_set_value(unsigned gpio, int value)
332{ 395{
333 u32 val; 396 struct u300_gpio *gpio = to_u300_gpio(chip);
334 unsigned long flags; 397 unsigned long flags;
398 u32 oldmode;
399 u32 val;
335 400
336 local_irq_save(flags); 401 local_irq_save(flags);
337 if (value) { 402 val = readl(U300_PIN_REG(offset, pcr));
338 /* set */ 403 /*
339 val = readl(virtbase + U300_GPIO_PXPDOR + 404 * Drive mode must be set by the special mode set function, set
340 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) 405 * push/pull mode by default if no mode has been selected.
341 & (1 << (gpio & 0x07)); 406 */
342 writel(val | (1 << (gpio & 0x07)), virtbase + 407 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
343 U300_GPIO_PXPDOR + 408 ((offset & 0x07) << 1));
344 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING); 409 /* mode = 0 means input, else some mode is already set */
345 } else { 410 if (oldmode == 0) {
346 /* clear */ 411 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
347 val = readl(virtbase + U300_GPIO_PXPDOR + 412 ((offset & 0x07) << 1));
348 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) 413 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
349 & (1 << (gpio & 0x07)); 414 << ((offset & 0x07) << 1));
350 writel(val & ~(1 << (gpio & 0x07)), virtbase + 415 writel(val, U300_PIN_REG(offset, pcr));
351 U300_GPIO_PXPDOR +
352 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
353 } 416 }
417 u300_gpio_set(chip, offset, value);
354 local_irq_restore(flags); 418 local_irq_restore(flags);
419 return 0;
355} 420}
356EXPORT_SYMBOL(gpio_set_value);
357 421
358int gpio_direction_input(unsigned gpio) 422static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
359{ 423{
424 struct u300_gpio *gpio = to_u300_gpio(chip);
425 int retirq = gpio->irq_base + offset;
426
427 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
428 retirq);
429 return retirq;
430}
431
432static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
433 u16 param, unsigned long *data)
434{
435 struct u300_gpio *gpio = to_u300_gpio(chip);
360 unsigned long flags; 436 unsigned long flags;
361 u32 val; 437 u32 val;
362 438
363 if (gpio > U300_GPIO_MAX)
364 return -EINVAL;
365
366 local_irq_save(flags); 439 local_irq_save(flags);
367 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 440 switch (param) {
368 U300_GPIO_PORTX_SPACING); 441 case GPIO_U300_CONFIG_BIAS_UNKNOWN:
369 /* Mask out this pin*/ 442 case GPIO_U300_CONFIG_BIAS_FLOAT:
370 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1)); 443 val = readl(U300_PIN_REG(offset, per));
371 /* This is not needed since it sets the bits to zero.*/ 444 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
372 /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */ 445 break;
373 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 446 case GPIO_U300_CONFIG_BIAS_PULL_UP:
374 U300_GPIO_PORTX_SPACING); 447 val = readl(U300_PIN_REG(offset, per));
448 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
449 break;
450 case GPIO_U300_CONFIG_DRIVE_PUSH_PULL:
451 val = readl(U300_PIN_REG(offset, pcr));
452 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
453 << ((offset & 0x07) << 1));
454 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
455 << ((offset & 0x07) << 1));
456 writel(val, U300_PIN_REG(offset, pcr));
457 break;
458 case GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN:
459 val = readl(U300_PIN_REG(offset, pcr));
460 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
461 << ((offset & 0x07) << 1));
462 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
463 << ((offset & 0x07) << 1));
464 writel(val, U300_PIN_REG(offset, pcr));
465 break;
466 case GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE:
467 val = readl(U300_PIN_REG(offset, pcr));
468 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
469 << ((offset & 0x07) << 1));
470 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
471 << ((offset & 0x07) << 1));
472 writel(val, U300_PIN_REG(offset, pcr));
473 break;
474 default:
475 local_irq_restore(flags);
476 dev_err(gpio->dev, "illegal configuration requested\n");
477 return -EINVAL;
478 }
375 local_irq_restore(flags); 479 local_irq_restore(flags);
376 return 0; 480 return 0;
377} 481}
378EXPORT_SYMBOL(gpio_direction_input);
379 482
380int gpio_direction_output(unsigned gpio, int value) 483static struct gpio_chip u300_gpio_chip = {
484 .label = "u300-gpio-chip",
485 .owner = THIS_MODULE,
486 .get = u300_gpio_get,
487 .set = u300_gpio_set,
488 .direction_input = u300_gpio_direction_input,
489 .direction_output = u300_gpio_direction_output,
490 .to_irq = u300_gpio_to_irq,
491};
492
493static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
381{ 494{
382 unsigned long flags;
383 u32 val; 495 u32 val;
384 496
385 if (gpio > U300_GPIO_MAX) 497 val = readl(U300_PIN_REG(offset, icr));
386 return -EINVAL; 498 /* Set mode depending on state */
387 499 if (u300_gpio_get(&gpio->chip, offset)) {
388 local_irq_save(flags); 500 /* High now, let's trigger on falling edge next then */
389 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 501 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
390 U300_GPIO_PORTX_SPACING); 502 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
391 /* Mask out this pin */ 503 offset);
392 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1)); 504 } else {
393 /* 505 /* Low now, let's trigger on rising edge next then */
394 * FIXME: configure for push/pull, open drain or open source per pin 506 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
395 * in setup. The current driver will only support push/pull. 507 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
396 */ 508 offset);
397 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 509 }
398 << ((gpio & 0x07) << 1));
399 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
400 U300_GPIO_PORTX_SPACING);
401 gpio_set_value(gpio, value);
402 local_irq_restore(flags);
403 return 0;
404} 510}
405EXPORT_SYMBOL(gpio_direction_output);
406 511
407/* 512static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
408 * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
409 */
410void enable_irq_on_gpio_pin(unsigned gpio, int edge)
411{ 513{
514 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
515 struct u300_gpio *gpio = port->gpio;
516 int offset = d->irq - gpio->irq_base;
412 u32 val; 517 u32 val;
413 unsigned long flags;
414 local_irq_save(flags);
415 518
416 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 519 if ((trigger & IRQF_TRIGGER_RISING) &&
417 U300_GPIO_PORTX_SPACING); 520 (trigger & IRQF_TRIGGER_FALLING)) {
418 val |= (1 << (gpio & 0x07)); 521 /*
419 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 522 * The GPIO block can only trigger on falling OR rising edges,
420 U300_GPIO_PORTX_SPACING); 523 * not both. So we need to toggle the mode whenever the pin
421 val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) * 524 * goes from one state to the other with a special state flag
422 U300_GPIO_PORTX_SPACING); 525 */
423 if (edge) 526 dev_dbg(gpio->dev,
424 val |= (1 << (gpio & 0x07)); 527 "trigger on both rising and falling edge on pin %d\n",
425 else 528 offset);
426 val &= ~(1 << (gpio & 0x07)); 529 port->toggle_edge_mode |= U300_PIN_BIT(offset);
427 writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) * 530 u300_toggle_trigger(gpio, offset);
428 U300_GPIO_PORTX_SPACING); 531 } else if (trigger & IRQF_TRIGGER_RISING) {
429 local_irq_restore(flags); 532 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
533 offset);
534 val = readl(U300_PIN_REG(offset, icr));
535 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
536 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
537 } else if (trigger & IRQF_TRIGGER_FALLING) {
538 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
539 offset);
540 val = readl(U300_PIN_REG(offset, icr));
541 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
542 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
543 }
544
545 return 0;
430} 546}
431EXPORT_SYMBOL(enable_irq_on_gpio_pin);
432 547
433void disable_irq_on_gpio_pin(unsigned gpio) 548static void u300_gpio_irq_enable(struct irq_data *d)
434{ 549{
550 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
551 struct u300_gpio *gpio = port->gpio;
552 int offset = d->irq - gpio->irq_base;
435 u32 val; 553 u32 val;
436 unsigned long flags; 554 unsigned long flags;
437 555
438 local_irq_save(flags); 556 local_irq_save(flags);
439 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 557 val = readl(U300_PIN_REG(offset, ien));
440 U300_GPIO_PORTX_SPACING); 558 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
441 val &= ~(1 << (gpio & 0x07));
442 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
443 U300_GPIO_PORTX_SPACING);
444 local_irq_restore(flags); 559 local_irq_restore(flags);
445} 560}
446EXPORT_SYMBOL(disable_irq_on_gpio_pin);
447 561
448/* Enable (value == 0) or disable (value == 1) internal pullup */ 562static void u300_gpio_irq_disable(struct irq_data *d)
449void gpio_pullup(unsigned gpio, int value)
450{ 563{
564 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
565 struct u300_gpio *gpio = port->gpio;
566 int offset = d->irq - gpio->irq_base;
451 u32 val; 567 u32 val;
452 unsigned long flags; 568 unsigned long flags;
453 569
454 local_irq_save(flags); 570 local_irq_save(flags);
455 if (value) { 571 val = readl(U300_PIN_REG(offset, ien));
456 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) * 572 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
457 U300_GPIO_PORTX_SPACING);
458 writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
459 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
460 } else {
461 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
462 U300_GPIO_PORTX_SPACING);
463 writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
464 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
465 }
466 local_irq_restore(flags); 573 local_irq_restore(flags);
467} 574}
468EXPORT_SYMBOL(gpio_pullup);
469 575
470static irqreturn_t gpio_irq_handler(int irq, void *dev_id) 576static struct irq_chip u300_gpio_irqchip = {
577 .name = "u300-gpio-irqchip",
578 .irq_enable = u300_gpio_irq_enable,
579 .irq_disable = u300_gpio_irq_disable,
580 .irq_set_type = u300_gpio_irq_type,
581
582};
583
584static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
471{ 585{
472 struct u300_gpio_port *port = dev_id; 586 struct u300_gpio_port *port = irq_get_handler_data(irq);
473 u32 val; 587 struct u300_gpio *gpio = port->gpio;
474 int pin; 588 int pinoffset = port->number << 3; /* get the right stride */
589 unsigned long val;
475 590
591 desc->irq_data.chip->irq_ack(&desc->irq_data);
476 /* Read event register */ 592 /* Read event register */
477 val = readl(virtbase + U300_GPIO_PXIEV + port->number * 593 val = readl(U300_PIN_REG(pinoffset, iev));
478 U300_GPIO_PORTX_SPACING);
479 /* Mask with enable register */
480 val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
481 U300_GPIO_PORTX_SPACING);
482 /* Mask relevant bits */ 594 /* Mask relevant bits */
483 val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK; 595 val &= 0xFFU; /* 8 bits per port */
484 /* ACK IRQ (clear event) */ 596 /* ACK IRQ (clear event) */
485 writel(val, virtbase + U300_GPIO_PXIEV + port->number * 597 writel(val, U300_PIN_REG(pinoffset, iev));
486 U300_GPIO_PORTX_SPACING); 598
487 /* Print message */ 599 /* Call IRQ handler */
488 while (val != 0) { 600 if (val != 0) {
489 unsigned gpio; 601 int irqoffset;
490 602
491 pin = __ffs(val); 603 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
492 /* mask off this pin */ 604 int pin_irq = gpio->irq_base + (port->number << 3)
493 val &= ~(1 << pin); 605 + irqoffset;
494 gpio = (port->number << 3) + pin; 606 int offset = pinoffset + irqoffset;
495 607
496 if (gpio_pin[gpio].callback) 608 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
497 (void)gpio_pin[gpio].callback(gpio_pin[gpio].data); 609 pin_irq, offset);
498 else 610 generic_handle_irq(pin_irq);
499 dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n", 611 /*
500 gpio); 612 * Triggering IRQ on both rising and falling edge
613 * needs mockery
614 */
615 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
616 u300_toggle_trigger(gpio, offset);
617 }
501 } 618 }
502 return IRQ_HANDLED; 619
620 desc->irq_data.chip->irq_unmask(&desc->irq_data);
503} 621}
504 622
505static void gpio_set_initial_values(void) 623static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
624 int offset,
625 const struct u300_gpio_confdata *conf)
506{ 626{
507#ifdef U300_COH901571_3 627 /* Set mode: input or output */
508 int i, j; 628 if (conf->output) {
509 unsigned long flags; 629 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
510 u32 val;
511 630
512 /* Write default values to all pins */ 631 /* Deactivate bias mode for output */
513 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 632 u300_gpio_config(&gpio->chip, offset,
514 val = 0; 633 GPIO_U300_CONFIG_BIAS_FLOAT,
515 for (j = 0; j < 8; j++) 634 NULL);
516 val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j; 635
517 local_irq_save(flags); 636 /* Set drive mode for output */
518 writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING); 637 u300_gpio_config(&gpio->chip, offset,
519 local_irq_restore(flags); 638 GPIO_U300_CONFIG_DRIVE_PUSH_PULL, NULL);
639
640 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
641 offset, conf->outval);
642 } else {
643 u300_gpio_direction_input(&gpio->chip, offset);
644
645 /* Always set output low on input pins */
646 u300_gpio_set(&gpio->chip, offset, 0);
647
648 /* Set bias mode for input */
649 u300_gpio_config(&gpio->chip, offset, conf->bias_mode, NULL);
650
651 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
652 offset, conf->bias_mode);
520 } 653 }
654}
521 655
522 /* 656static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
523 * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED' 657 struct u300_gpio_platform *plat)
524 * to output and 'GPIO_IN' to input for each port. And initialize 658{
525 * default value on outputs. 659 int i, j;
526 */ 660
527 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 661 /* Write default config and values to all pins */
528 for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) { 662 for (i = 0; i < plat->ports; i++) {
529 local_irq_save(flags); 663 for (j = 0; j < 8; j++) {
530 val = readl(virtbase + U300_GPIO_PXPCR + 664 const struct u300_gpio_confdata *conf;
531 i * U300_GPIO_PORTX_SPACING); 665 int offset = (i*8) + j;
532 /* Mask out this pin */ 666
533 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1)); 667 if (plat->variant == U300_GPIO_COH901571_3_BS335)
534 668 conf = &bs335_gpio_config[i][j];
535 if (u300_gpio_config[i][j].pin_usage != GPIO_IN) 669 else if (plat->variant == U300_GPIO_COH901571_3_BS365)
536 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1)); 670 conf = &bs365_gpio_config[i][j];
537 writel(val, virtbase + U300_GPIO_PXPCR + 671 else
538 i * U300_GPIO_PORTX_SPACING); 672 break;
539 local_irq_restore(flags); 673
674 u300_gpio_init_pin(gpio, offset, conf);
540 } 675 }
541 } 676 }
677}
542 678
543 /* Enable or disable the internal pull-ups in the GPIO ASIC block */ 679static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
544 for (i = 0; i < U300_GPIO_MAX; i++) { 680{
545 val = 0; 681 struct u300_gpio_port *port;
546 for (j = 0; j < 8; j++) 682 struct list_head *p, *n;
547 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j); 683
548 local_irq_save(flags); 684 list_for_each_safe(p, n, &gpio->port_list) {
549 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING); 685 port = list_entry(p, struct u300_gpio_port, node);
550 local_irq_restore(flags); 686 list_del(&port->node);
687 free_irq(port->irq, port);
688 kfree(port);
551 } 689 }
552#endif
553} 690}
554 691
555static int __init gpio_probe(struct platform_device *pdev) 692static int __init u300_gpio_probe(struct platform_device *pdev)
556{ 693{
557 u32 val; 694 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
695 struct u300_gpio *gpio;
558 int err = 0; 696 int err = 0;
697 int portno;
698 u32 val;
699 u32 ifr;
559 int i; 700 int i;
560 int num_irqs;
561 701
562 gpiodev = &pdev->dev; 702 gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
563 memset(gpio_pin, 0, sizeof(gpio_pin)); 703 if (gpio == NULL) {
704 dev_err(&pdev->dev, "failed to allocate memory\n");
705 return -ENOMEM;
706 }
707
708 gpio->chip = u300_gpio_chip;
709 gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
710 gpio->irq_base = plat->gpio_irq_base;
711 gpio->chip.dev = &pdev->dev;
712 gpio->chip.base = plat->gpio_base;
713 gpio->dev = &pdev->dev;
564 714
565 /* Get GPIO clock */ 715 /* Get GPIO clock */
566 clk = clk_get(&pdev->dev, NULL); 716 gpio->clk = clk_get(gpio->dev, NULL);
567 if (IS_ERR(clk)) { 717 if (IS_ERR(gpio->clk)) {
568 err = PTR_ERR(clk); 718 err = PTR_ERR(gpio->clk);
569 dev_err(gpiodev, "could not get GPIO clock\n"); 719 dev_err(gpio->dev, "could not get GPIO clock\n");
570 goto err_no_clk; 720 goto err_no_clk;
571 } 721 }
572 err = clk_enable(clk); 722 err = clk_enable(gpio->clk);
573 if (err) { 723 if (err) {
574 dev_err(gpiodev, "could not enable GPIO clock\n"); 724 dev_err(gpio->dev, "could not enable GPIO clock\n");
575 goto err_no_clk_enable; 725 goto err_no_clk_enable;
576 } 726 }
577 727
578 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 728 gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
579 if (!memres) 729 if (!gpio->memres) {
730 dev_err(gpio->dev, "could not get GPIO memory resource\n");
731 err = -ENODEV;
580 goto err_no_resource; 732 goto err_no_resource;
733 }
581 734
582 if (!request_mem_region(memres->start, resource_size(memres), 735 if (!request_mem_region(gpio->memres->start,
736 resource_size(gpio->memres),
583 "GPIO Controller")) { 737 "GPIO Controller")) {
584 err = -ENODEV; 738 err = -ENODEV;
585 goto err_no_ioregion; 739 goto err_no_ioregion;
586 } 740 }
587 741
588 virtbase = ioremap(memres->start, resource_size(memres)); 742 gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
589 if (!virtbase) { 743 if (!gpio->base) {
590 err = -ENOMEM; 744 err = -ENOMEM;
591 goto err_no_ioremap; 745 goto err_no_ioremap;
592 } 746 }
593 dev_info(gpiodev, "remapped 0x%08x to %p\n", 747
594 memres->start, virtbase); 748 if (plat->variant == U300_GPIO_COH901335) {
595 749 dev_info(gpio->dev,
596#ifdef U300_COH901335 750 "initializing GPIO Controller COH 901 335\n");
597 dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n"); 751 gpio->stride = U300_335_PORT_STRIDE;
598 /* Turn on the GPIO block */ 752 gpio->pcr = U300_335_PXPCR;
599 writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR); 753 gpio->dor = U300_335_PXPDOR;
600#endif 754 gpio->dir = U300_335_PXPDIR;
601 755 gpio->per = U300_335_PXPER;
602#ifdef U300_COH901571_3 756 gpio->icr = U300_335_PXICR;
603 dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n"); 757 gpio->ien = U300_335_PXIEN;
604 val = readl(virtbase + U300_GPIO_CR); 758 gpio->iev = U300_335_PXIEV;
605 dev_info(gpiodev, "COH901571/3 block version: %d, " \ 759 ifr = U300_335_PXIFR;
606 "number of cores: %d\n", 760
607 ((val & 0x0000FE00) >> 9), 761 /* Turn on the GPIO block */
608 ((val & 0x000001FC) >> 2)); 762 writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
609 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR); 763 gpio->base + U300_335_CR);
610#endif 764 } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
611 765 plat->variant == U300_GPIO_COH901571_3_BS365) {
612 gpio_set_initial_values(); 766 dev_info(gpio->dev,
613 767 "initializing GPIO Controller COH 901 571/3\n");
614 for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) { 768 gpio->stride = U300_571_PORT_STRIDE;
615 769 gpio->pcr = U300_571_PXPCR;
616 gpio_ports[num_irqs].irq = 770 gpio->dor = U300_571_PXPDOR;
617 platform_get_irq_byname(pdev, 771 gpio->dir = U300_571_PXPDIR;
618 gpio_ports[num_irqs].name); 772 gpio->per = U300_571_PXPER;
619 773 gpio->icr = U300_571_PXICR;
620 err = request_irq(gpio_ports[num_irqs].irq, 774 gpio->ien = U300_571_PXIEN;
621 gpio_irq_handler, IRQF_DISABLED, 775 gpio->iev = U300_571_PXIEV;
622 gpio_ports[num_irqs].name, 776 ifr = U300_571_PXIFR;
623 &gpio_ports[num_irqs]); 777
624 if (err) { 778 val = readl(gpio->base + U300_571_CR);
625 dev_err(gpiodev, "cannot allocate IRQ for %s!\n", 779 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
626 gpio_ports[num_irqs].name); 780 "number of cores: %d totalling %d pins\n",
627 goto err_no_irq; 781 ((val & 0x000001FC) >> 2),
782 ((val & 0x0000FE00) >> 9),
783 ((val & 0x0000FE00) >> 9) * 8);
784 writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
785 gpio->base + U300_571_CR);
786 u300_gpio_init_coh901571(gpio, plat);
787 } else {
788 dev_err(gpio->dev, "unknown block variant\n");
789 err = -ENODEV;
790 goto err_unknown_variant;
791 }
792
793 /* Add each port with its IRQ separately */
794 INIT_LIST_HEAD(&gpio->port_list);
795 for (portno = 0 ; portno < plat->ports; portno++) {
796 struct u300_gpio_port *port =
797 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
798
799 if (!port) {
800 dev_err(gpio->dev, "out of memory\n");
801 err = -ENOMEM;
802 goto err_no_port;
628 } 803 }
629 /* Turns off PortX_irq_force */ 804
630 writel(0x0, virtbase + U300_GPIO_PXIFR + 805 snprintf(port->name, 8, "gpio%d", portno);
631 num_irqs * U300_GPIO_PORTX_SPACING); 806 port->number = portno;
807 port->gpio = gpio;
808
809 port->irq = platform_get_irq_byname(pdev,
810 port->name);
811
812 dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
813 port->name);
814
815 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
816 irq_set_handler_data(port->irq, port);
817
818 /* For each GPIO pin set the unique IRQ handler */
819 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
820 int irqno = gpio->irq_base + (portno << 3) + i;
821
822 dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
823 irqno, port->name);
824 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
825 handle_simple_irq);
826 set_irq_flags(irqno, IRQF_VALID);
827 irq_set_chip_data(irqno, port);
828 }
829
830 /* Turns off irq force (test register) for this port */
831 writel(0x0, gpio->base + portno * gpio->stride + ifr);
832
833 list_add_tail(&port->node, &gpio->port_list);
632 } 834 }
835 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
836
837 err = gpiochip_add(&gpio->chip);
838 if (err) {
839 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
840 goto err_no_chip;
841 }
842
843 platform_set_drvdata(pdev, gpio);
633 844
634 return 0; 845 return 0;
635 846
636 err_no_irq: 847err_no_chip:
637 for (i = 0; i < num_irqs; i++) 848err_no_port:
638 free_irq(gpio_ports[i].irq, &gpio_ports[i]); 849 u300_gpio_free_ports(gpio);
639 iounmap(virtbase); 850err_unknown_variant:
640 err_no_ioremap: 851 iounmap(gpio->base);
641 release_mem_region(memres->start, resource_size(memres)); 852err_no_ioremap:
642 err_no_ioregion: 853 release_mem_region(gpio->memres->start, resource_size(gpio->memres));
643 err_no_resource: 854err_no_ioregion:
644 clk_disable(clk); 855err_no_resource:
645 err_no_clk_enable: 856 clk_disable(gpio->clk);
646 clk_put(clk); 857err_no_clk_enable:
647 err_no_clk: 858 clk_put(gpio->clk);
648 dev_info(gpiodev, "module ERROR:%d\n", err); 859err_no_clk:
860 kfree(gpio);
861 dev_info(&pdev->dev, "module ERROR:%d\n", err);
649 return err; 862 return err;
650} 863}
651 864
652static int __exit gpio_remove(struct platform_device *pdev) 865static int __exit u300_gpio_remove(struct platform_device *pdev)
653{ 866{
654 int i; 867 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
868 struct u300_gpio *gpio = platform_get_drvdata(pdev);
869 int err;
655 870
656 /* Turn off the GPIO block */ 871 /* Turn off the GPIO block */
657 writel(0x00000000U, virtbase + U300_GPIO_CR); 872 if (plat->variant == U300_GPIO_COH901335)
658 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++) 873 writel(0x00000000U, gpio->base + U300_335_CR);
659 free_irq(gpio_ports[i].irq, &gpio_ports[i]); 874 if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
660 iounmap(virtbase); 875 plat->variant == U300_GPIO_COH901571_3_BS365)
661 release_mem_region(memres->start, resource_size(memres)); 876 writel(0x00000000U, gpio->base + U300_571_CR);
662 clk_disable(clk); 877
663 clk_put(clk); 878 err = gpiochip_remove(&gpio->chip);
879 if (err < 0) {
880 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
881 return err;
882 }
883 u300_gpio_free_ports(gpio);
884 iounmap(gpio->base);
885 release_mem_region(gpio->memres->start,
886 resource_size(gpio->memres));
887 clk_disable(gpio->clk);
888 clk_put(gpio->clk);
889 platform_set_drvdata(pdev, NULL);
890 kfree(gpio);
664 return 0; 891 return 0;
665} 892}
666 893
667static struct platform_driver gpio_driver = { 894static struct platform_driver u300_gpio_driver = {
668 .driver = { 895 .driver = {
669 .name = "u300-gpio", 896 .name = "u300-gpio",
670 }, 897 },
671 .remove = __exit_p(gpio_remove), 898 .remove = __exit_p(u300_gpio_remove),
672}; 899};
673 900
674 901
675static int __init u300_gpio_init(void) 902static int __init u300_gpio_init(void)
676{ 903{
677 return platform_driver_probe(&gpio_driver, gpio_probe); 904 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
678} 905}
679 906
680static void __exit u300_gpio_exit(void) 907static void __exit u300_gpio_exit(void)
681{ 908{
682 platform_driver_unregister(&gpio_driver); 909 platform_driver_unregister(&u300_gpio_driver);
683} 910}
684 911
685arch_initcall(u300_gpio_init); 912arch_initcall(u300_gpio_init);
686module_exit(u300_gpio_exit); 913module_exit(u300_gpio_exit);
687 914
688MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 915MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
689 916MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
690#ifdef U300_COH901571_3
691MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
692#endif
693
694#ifdef U300_COH901335
695MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
696#endif
697
698MODULE_LICENSE("GPL"); 917MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-17 04:05:58 -0400