Merge branch 'pci/yijing-mps-v1' into next

* pci/yijing-mps-v1:
  drm/radeon: use pcie_get_readrq() and pcie_set_readrq() to simplify code
  staging: et131x: Use pci_dev->pcie_mpss and pcie_set_readrq() to simplify code
  IB/qib: Drop qib_tune_pcie_caps() and qib_tune_pcie_coalesce() return values
  IB/qib: Use pcie_set_mps() and pcie_get_mps() to simplify code
  IB/qib: Use pci_is_root_bus() to check whether it is a root bus
  tile/PCI: use cached pci_dev->pcie_mpss to simplify code
  PCI: Export pcie_set_mps() and pcie_get_mps()

5 files changed, 56 insertions, 112 deletions

diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index b7180e6e900d..c45593db7718 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -251,15 +251,12 @@ static void fixup_read_and_payload_sizes(void)
         /* Scan for the smallest maximum payload size. */
         for_each_pci_dev(dev) {
                 u32 devcap;
-                int max_payload;
 
                 if (!pci_is_pcie(dev))
                         continue;
 
-                pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
-                max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
-                if (max_payload < smallest_max_payload)
-                        smallest_max_payload = max_payload;
+                if (dev->pcie_mpss < smallest_max_payload)
+                        smallest_max_payload = dev->pcie_mpss;
         }
 
         /* Now, set the max_payload_size for all devices to that value. */
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 555164e270a7..871066a8c630 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1174,23 +1174,16 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 
 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
 {
-        u16 ctl, v;
-        int err;
-
-        err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
-        if (err)
-                return;
-
-        v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
+        int readrq;
+        u16 v;
 
+        readrq = pcie_get_readrq(rdev->pdev);
+        v = ffs(readrq) - 8;
         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
          * to avoid hangs or perfomance issues
          */
-        if ((v == 0) || (v == 6) || (v == 7)) {
-                ctl &= ~PCI_EXP_DEVCTL_READRQ;
-                ctl |= (2 << 12);
-                pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
-        }
+        if ((v == 0) || (v == 6) || (v == 7))
+                pcie_set_readrq(rdev->pdev, 512);
 }
 
 static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
diff --git a/drivers/infiniband/hw/qib/qib_pcie.c b/drivers/infiniband/hw/qib/qib_pcie.c
index 3f14009fb662..c8d9c4ab142b 100644
--- a/drivers/infiniband/hw/qib/qib_pcie.c
+++ b/drivers/infiniband/hw/qib/qib_pcie.c
@@ -51,8 +51,8 @@
  * file calls, even though this violates some
  * expectations of harmlessness.
  */
-static int qib_tune_pcie_caps(struct qib_devdata *);
-static int qib_tune_pcie_coalesce(struct qib_devdata *);
+static void qib_tune_pcie_caps(struct qib_devdata *);
+static void qib_tune_pcie_coalesce(struct qib_devdata *);
 
 /*
  * Do all the common PCIe setup and initialization.
@@ -476,30 +476,6 @@ void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
                         "pci_enable_device failed after reset: %d\n", r);
 }
 
-/* code to adjust PCIe capabilities. */
-
-static int fld2val(int wd, int mask)
-{
-        int lsbmask;
-
-        if (!mask)
-                return 0;
-        wd &= mask;
-        lsbmask = mask ^ (mask & (mask - 1));
-        wd /= lsbmask;
-        return wd;
-}
-
-static int val2fld(int wd, int mask)
-{
-        int lsbmask;
-
-        if (!mask)
-                return 0;
-        lsbmask = mask ^ (mask & (mask - 1));
-        wd *= lsbmask;
-        return wd;
-}
 
 static int qib_pcie_coalesce;
 module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
@@ -511,7 +487,7 @@ MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets");
  * of these chipsets, with some BIOS settings, and enabling it on those
  * systems may result in the system crashing, and/or data corruption.
  */
-static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
+static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
 {
         int r;
         struct pci_dev *parent;
@@ -519,18 +495,18 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
         u32 mask, bits, val;
 
         if (!qib_pcie_coalesce)
-                return 0;
+                return;
 
         /* Find out supported and configured values for parent (root) */
         parent = dd->pcidev->bus->self;
         if (parent->bus->parent) {
                 qib_devinfo(dd->pcidev, "Parent not root\n");
-                return 1;
+                return;
         }
         if (!pci_is_pcie(parent))
-                return 1;
+                return;
         if (parent->vendor != 0x8086)
-                return 1;
+                return;
 
         /*
          *  - bit 12: Max_rdcmp_Imt_EN: need to set to 1
@@ -563,13 +539,12 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
                 mask = (3U << 24) | (7U << 10);
         } else {
                 /* not one of the chipsets that we know about */
-                return 1;
+                return;
         }
         pci_read_config_dword(parent, 0x48, &val);
         val &= ~mask;
         val |= bits;
         r = pci_write_config_dword(parent, 0x48, val);
-        return 0;
 }
 
 /*
@@ -580,55 +555,44 @@ static int qib_pcie_caps;
 module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
 
-static int qib_tune_pcie_caps(struct qib_devdata *dd)
+static void qib_tune_pcie_caps(struct qib_devdata *dd)
 {
-        int ret = 1; /* Assume the worst */
         struct pci_dev *parent;
-        u16 pcaps, pctl, ecaps, ectl;
-        int rc_sup, ep_sup;
-        int rc_cur, ep_cur;
+        u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
+        u16 rc_mrrs, ep_mrrs, max_mrrs;
 
         /* Find out supported and configured values for parent (root) */
         parent = dd->pcidev->bus->self;
-        if (parent->bus->parent) {
+        if (!pci_is_root_bus(parent->bus)) {
                 qib_devinfo(dd->pcidev, "Parent not root\n");
-                goto bail;
+                return;
         }
 
         if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
-                goto bail;
-        pcie_capability_read_word(parent, PCI_EXP_DEVCAP, &pcaps);
-        pcie_capability_read_word(parent, PCI_EXP_DEVCTL, &pctl);
+                return;
+
+        rc_mpss = parent->pcie_mpss;
+        rc_mps = ffs(pcie_get_mps(parent)) - 8;
         /* Find out supported and configured values for endpoint (us) */
-        pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCAP, &ecaps);
-        pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
+        ep_mpss = dd->pcidev->pcie_mpss;
+        ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
 
-        ret = 0;
         /* Find max payload supported by root, endpoint */
-        rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD);
-        ep_sup = fld2val(ecaps, PCI_EXP_DEVCAP_PAYLOAD);
-        if (rc_sup > ep_sup)
-                rc_sup = ep_sup;
-
-        rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_PAYLOAD);
-        ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_PAYLOAD);
+        if (rc_mpss > ep_mpss)
+                rc_mpss = ep_mpss;
 
         /* If Supported greater than limit in module param, limit it */
-        if (rc_sup > (qib_pcie_caps & 7))
-                rc_sup = qib_pcie_caps & 7;
+        if (rc_mpss > (qib_pcie_caps & 7))
+                rc_mpss = qib_pcie_caps & 7;
         /* If less than (allowed, supported), bump root payload */
-        if (rc_sup > rc_cur) {
-                rc_cur = rc_sup;
-                pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) |
-                        val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
-                pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
+        if (rc_mpss > rc_mps) {
+                rc_mps = rc_mpss;
+                pcie_set_mps(parent, 128 << rc_mps);
         }
         /* If less than (allowed, supported), bump endpoint payload */
-        if (rc_sup > ep_cur) {
-                ep_cur = rc_sup;
-                ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) |
-                        val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
-                pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
+        if (rc_mpss > ep_mps) {
+                ep_mps = rc_mpss;
+                pcie_set_mps(dd->pcidev, 128 << ep_mps);
         }
 
         /*
@@ -636,26 +600,22 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
          * No field for max supported, but PCIe spec limits it to 4096,
          * which is code '5' (log2(4096) - 7)
          */
-        rc_sup = 5;
-        if (rc_sup > ((qib_pcie_caps >> 4) & 7))
-                rc_sup = (qib_pcie_caps >> 4) & 7;
-        rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_READRQ);
-        ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_READRQ);
-
-        if (rc_sup > rc_cur) {
-                rc_cur = rc_sup;
-                pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) |
-                        val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
-                pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
+        max_mrrs = 5;
+        if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
+                max_mrrs = (qib_pcie_caps >> 4) & 7;
+
+        max_mrrs = 128 << max_mrrs;
+        rc_mrrs = pcie_get_readrq(parent);
+        ep_mrrs = pcie_get_readrq(dd->pcidev);
+
+        if (max_mrrs > rc_mrrs) {
+                rc_mrrs = max_mrrs;
+                pcie_set_readrq(parent, rc_mrrs);
         }
-        if (rc_sup > ep_cur) {
-                ep_cur = rc_sup;
-                ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) |
-                        val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
-                pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
+        if (max_mrrs > ep_mrrs) {
+                ep_mrrs = max_mrrs;
+                pcie_set_readrq(dd->pcidev, ep_mrrs);
         }
-bail:
-        return ret;
 }
 /* End of PCIe capability tuning */
 
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index ad7fc72a40a0..c0805f26f339 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3972,6 +3972,7 @@ int pcie_get_mps(struct pci_dev *dev)
 
         return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
 }
+EXPORT_SYMBOL(pcie_get_mps);
 
 /**
  * pcie_set_mps - set PCI Express maximum payload size
@@ -3996,6 +3997,7 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
         return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
                                                   PCI_EXP_DEVCTL_PAYLOAD, v);
 }
+EXPORT_SYMBOL(pcie_set_mps);
 
 /**
  * pcie_get_minimum_link - determine minimum link settings of a PCI device
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index f73e58f5ef8d..876881d1826e 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -3605,17 +3605,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
                 goto err_out;
         }
 
-        /* Let's set up the PORT LOGIC Register.  First we need to know what
-         * the max_payload_size is
-         */
-        if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
-                dev_err(&pdev->dev,
-                    "Could not read PCI config space for Max Payload Size\n");
-                goto err_out;
-        }
+        /* Let's set up the PORT LOGIC Register. */
 
         /* Program the Ack/Nak latency and replay timers */
-        max_payload &= 0x07;
+        max_payload = pdev->pcie_mpss;
 
         if (max_payload < 2) {
                 static const u16 acknak[2] = { 0x76, 0xD0 };
@@ -3645,8 +3638,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
         }
 
         /* Change the max read size to 2k */
-        if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
-                                PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {
+        if (pcie_set_readrq(pdev, 2048)) {
                 dev_err(&pdev->dev,
                         "Couldn't change PCI config space for Max read size\n");
                 goto err_out;