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authorAndi Kleen <ak@linux.intel.com>2011-10-13 19:08:46 -0400
committerDave Airlie <airlied@redhat.com>2011-10-18 04:44:52 -0400
commitcbdd45015af78ec9e75ed7a3df8b76048c4d289f (patch)
treecdce13ec47ded1f53cc450e7aba53a642e9f0130
parent6a2f371d718b76669dea772d32e6d4703f7eb0e4 (diff)
drm/radeon: Remove more bogus inlines in the radeon driver.
Remove bogus inlines in evergreen and r100. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c4
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c2
-rw-r--r--drivers/gpu/drm/radeon/r100.c106
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h110
4 files changed, 114 insertions, 108 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 5df39bf9ee49..562f9a3a69f1 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2633,7 +2633,7 @@ int evergreen_irq_set(struct radeon_device *rdev)
2633 return 0; 2633 return 0;
2634} 2634}
2635 2635
2636static inline void evergreen_irq_ack(struct radeon_device *rdev) 2636static void evergreen_irq_ack(struct radeon_device *rdev)
2637{ 2637{
2638 u32 tmp; 2638 u32 tmp;
2639 2639
@@ -2744,7 +2744,7 @@ void evergreen_irq_suspend(struct radeon_device *rdev)
2744 r600_rlc_stop(rdev); 2744 r600_rlc_stop(rdev);
2745} 2745}
2746 2746
2747static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev) 2747static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2748{ 2748{
2749 u32 wptr, tmp; 2749 u32 wptr, tmp;
2750 2750
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index 2eb251858e72..7eb78b3b30b7 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -584,7 +584,7 @@ set_default_state(struct radeon_device *rdev)
584 584
585} 585}
586 586
587static inline uint32_t i2f(uint32_t input) 587static uint32_t i2f(uint32_t input)
588{ 588{
589 u32 result, i, exponent, fraction; 589 u32 result, i, exponent, fraction;
590 590
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 574f2c7c6dd9..13c0169e70ac 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -68,6 +68,108 @@ MODULE_FIRMWARE(FIRMWARE_R520);
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 */ 69 */
70 70
71int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
72 struct radeon_cs_packet *pkt,
73 unsigned idx,
74 unsigned reg)
75{
76 int r;
77 u32 tile_flags = 0;
78 u32 tmp;
79 struct radeon_cs_reloc *reloc;
80 u32 value;
81
82 r = r100_cs_packet_next_reloc(p, &reloc);
83 if (r) {
84 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
85 idx, reg);
86 r100_cs_dump_packet(p, pkt);
87 return r;
88 }
89 value = radeon_get_ib_value(p, idx);
90 tmp = value & 0x003fffff;
91 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
92
93 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
94 tile_flags |= RADEON_DST_TILE_MACRO;
95 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
96 if (reg == RADEON_SRC_PITCH_OFFSET) {
97 DRM_ERROR("Cannot src blit from microtiled surface\n");
98 r100_cs_dump_packet(p, pkt);
99 return -EINVAL;
100 }
101 tile_flags |= RADEON_DST_TILE_MICRO;
102 }
103
104 tmp |= tile_flags;
105 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
106 return 0;
107}
108
109int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
110 struct radeon_cs_packet *pkt,
111 int idx)
112{
113 unsigned c, i;
114 struct radeon_cs_reloc *reloc;
115 struct r100_cs_track *track;
116 int r = 0;
117 volatile uint32_t *ib;
118 u32 idx_value;
119
120 ib = p->ib->ptr;
121 track = (struct r100_cs_track *)p->track;
122 c = radeon_get_ib_value(p, idx++) & 0x1F;
123 if (c > 16) {
124 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
125 pkt->opcode);
126 r100_cs_dump_packet(p, pkt);
127 return -EINVAL;
128 }
129 track->num_arrays = c;
130 for (i = 0; i < (c - 1); i+=2, idx+=3) {
131 r = r100_cs_packet_next_reloc(p, &reloc);
132 if (r) {
133 DRM_ERROR("No reloc for packet3 %d\n",
134 pkt->opcode);
135 r100_cs_dump_packet(p, pkt);
136 return r;
137 }
138 idx_value = radeon_get_ib_value(p, idx);
139 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
140
141 track->arrays[i + 0].esize = idx_value >> 8;
142 track->arrays[i + 0].robj = reloc->robj;
143 track->arrays[i + 0].esize &= 0x7F;
144 r = r100_cs_packet_next_reloc(p, &reloc);
145 if (r) {
146 DRM_ERROR("No reloc for packet3 %d\n",
147 pkt->opcode);
148 r100_cs_dump_packet(p, pkt);
149 return r;
150 }
151 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
152 track->arrays[i + 1].robj = reloc->robj;
153 track->arrays[i + 1].esize = idx_value >> 24;
154 track->arrays[i + 1].esize &= 0x7F;
155 }
156 if (c & 1) {
157 r = r100_cs_packet_next_reloc(p, &reloc);
158 if (r) {
159 DRM_ERROR("No reloc for packet3 %d\n",
160 pkt->opcode);
161 r100_cs_dump_packet(p, pkt);
162 return r;
163 }
164 idx_value = radeon_get_ib_value(p, idx);
165 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
166 track->arrays[i + 0].robj = reloc->robj;
167 track->arrays[i + 0].esize = idx_value >> 8;
168 track->arrays[i + 0].esize &= 0x7F;
169 }
170 return r;
171}
172
71void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 173void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
72{ 174{
73 /* enable the pflip int */ 175 /* enable the pflip int */
@@ -591,7 +693,7 @@ void r100_irq_disable(struct radeon_device *rdev)
591 WREG32(R_000044_GEN_INT_STATUS, tmp); 693 WREG32(R_000044_GEN_INT_STATUS, tmp);
592} 694}
593 695
594static inline uint32_t r100_irq_ack(struct radeon_device *rdev) 696static uint32_t r100_irq_ack(struct radeon_device *rdev)
595{ 697{
596 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 698 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
597 uint32_t irq_mask = RADEON_SW_INT_TEST | 699 uint32_t irq_mask = RADEON_SW_INT_TEST |
@@ -3152,7 +3254,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
3152 } 3254 }
3153} 3255}
3154 3256
3155static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 3257static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3156{ 3258{
3157 DRM_ERROR("pitch %d\n", t->pitch); 3259 DRM_ERROR("pitch %d\n", t->pitch);
3158 DRM_ERROR("use_pitch %d\n", t->use_pitch); 3260 DRM_ERROR("use_pitch %d\n", t->use_pitch);
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 686f9dc5d4bd..6a603b378adb 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -92,106 +92,10 @@ int r200_packet0_check(struct radeon_cs_parser *p,
92 struct radeon_cs_packet *pkt, 92 struct radeon_cs_packet *pkt,
93 unsigned idx, unsigned reg); 93 unsigned idx, unsigned reg);
94 94
95 95int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
96 96 struct radeon_cs_packet *pkt,
97static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 97 unsigned idx,
98 struct radeon_cs_packet *pkt, 98 unsigned reg);
99 unsigned idx, 99int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
100 unsigned reg) 100 struct radeon_cs_packet *pkt,
101{ 101 int idx);
102 int r;
103 u32 tile_flags = 0;
104 u32 tmp;
105 struct radeon_cs_reloc *reloc;
106 u32 value;
107
108 r = r100_cs_packet_next_reloc(p, &reloc);
109 if (r) {
110 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
111 idx, reg);
112 r100_cs_dump_packet(p, pkt);
113 return r;
114 }
115 value = radeon_get_ib_value(p, idx);
116 tmp = value & 0x003fffff;
117 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
118
119 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
120 tile_flags |= RADEON_DST_TILE_MACRO;
121 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
122 if (reg == RADEON_SRC_PITCH_OFFSET) {
123 DRM_ERROR("Cannot src blit from microtiled surface\n");
124 r100_cs_dump_packet(p, pkt);
125 return -EINVAL;
126 }
127 tile_flags |= RADEON_DST_TILE_MICRO;
128 }
129
130 tmp |= tile_flags;
131 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
132 return 0;
133}
134
135static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
136 struct radeon_cs_packet *pkt,
137 int idx)
138{
139 unsigned c, i;
140 struct radeon_cs_reloc *reloc;
141 struct r100_cs_track *track;
142 int r = 0;
143 volatile uint32_t *ib;
144 u32 idx_value;
145
146 ib = p->ib->ptr;
147 track = (struct r100_cs_track *)p->track;
148 c = radeon_get_ib_value(p, idx++) & 0x1F;
149 if (c > 16) {
150 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
151 pkt->opcode);
152 r100_cs_dump_packet(p, pkt);
153 return -EINVAL;
154 }
155 track->num_arrays = c;
156 for (i = 0; i < (c - 1); i+=2, idx+=3) {
157 r = r100_cs_packet_next_reloc(p, &reloc);
158 if (r) {
159 DRM_ERROR("No reloc for packet3 %d\n",
160 pkt->opcode);
161 r100_cs_dump_packet(p, pkt);
162 return r;
163 }
164 idx_value = radeon_get_ib_value(p, idx);
165 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
166
167 track->arrays[i + 0].esize = idx_value >> 8;
168 track->arrays[i + 0].robj = reloc->robj;
169 track->arrays[i + 0].esize &= 0x7F;
170 r = r100_cs_packet_next_reloc(p, &reloc);
171 if (r) {
172 DRM_ERROR("No reloc for packet3 %d\n",
173 pkt->opcode);
174 r100_cs_dump_packet(p, pkt);
175 return r;
176 }
177 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
178 track->arrays[i + 1].robj = reloc->robj;
179 track->arrays[i + 1].esize = idx_value >> 24;
180 track->arrays[i + 1].esize &= 0x7F;
181 }
182 if (c & 1) {
183 r = r100_cs_packet_next_reloc(p, &reloc);
184 if (r) {
185 DRM_ERROR("No reloc for packet3 %d\n",
186 pkt->opcode);
187 r100_cs_dump_packet(p, pkt);
188 return r;
189 }
190 idx_value = radeon_get_ib_value(p, idx);
191 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
192 track->arrays[i + 0].robj = reloc->robj;
193 track->arrays[i + 0].esize = idx_value >> 8;
194 track->arrays[i + 0].esize &= 0x7F;
195 }
196 return r;
197}
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