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authorShawn Guo <shawn.guo@linaro.org>2012-09-17 03:12:28 -0400
committerShawn Guo <shawn.guo@linaro.org>2012-09-17 03:12:28 -0400
commitcb32b4e0fc53ebd45708dd7aa8d7fa224e97308c (patch)
tree68b8015b5e0ba3acb69db4f1c458841d327e74fe
parentb1f174b19c15e36a5e6f209d98caba77385d790e (diff)
parent0e87e0436c0cc3954eb62181a96d7217ca955a4f (diff)
Merge tag 'imx-clk-dt-lookup' into imx/dt-for-3.7-2
Conflicts: arch/arm/boot/dts/imx6q.dtsi
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt222
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts1
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi73
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c44
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c1
5 files changed, 291 insertions, 50 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
new file mode 100644
index 000000000000..492bd991d52a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -0,0 +1,222 @@
1* Clock bindings for Freescale i.MX6 Quad
2
3Required properties:
4- compatible: Should be "fsl,imx6q-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 ckih 2
18 osc 3
19 pll2_pfd0_352m 4
20 pll2_pfd1_594m 5
21 pll2_pfd2_396m 6
22 pll3_pfd0_720m 7
23 pll3_pfd1_540m 8
24 pll3_pfd2_508m 9
25 pll3_pfd3_454m 10
26 pll2_198m 11
27 pll3_120m 12
28 pll3_80m 13
29 pll3_60m 14
30 twd 15
31 step 16
32 pll1_sw 17
33 periph_pre 18
34 periph2_pre 19
35 periph_clk2_sel 20
36 periph2_clk2_sel 21
37 axi_sel 22
38 esai_sel 23
39 asrc_sel 24
40 spdif_sel 25
41 gpu2d_axi 26
42 gpu3d_axi 27
43 gpu2d_core_sel 28
44 gpu3d_core_sel 29
45 gpu3d_shader_sel 30
46 ipu1_sel 31
47 ipu2_sel 32
48 ldb_di0_sel 33
49 ldb_di1_sel 34
50 ipu1_di0_pre_sel 35
51 ipu1_di1_pre_sel 36
52 ipu2_di0_pre_sel 37
53 ipu2_di1_pre_sel 38
54 ipu1_di0_sel 39
55 ipu1_di1_sel 40
56 ipu2_di0_sel 41
57 ipu2_di1_sel 42
58 hsi_tx_sel 43
59 pcie_axi_sel 44
60 ssi1_sel 45
61 ssi2_sel 46
62 ssi3_sel 47
63 usdhc1_sel 48
64 usdhc2_sel 49
65 usdhc3_sel 50
66 usdhc4_sel 51
67 enfc_sel 52
68 emi_sel 53
69 emi_slow_sel 54
70 vdo_axi_sel 55
71 vpu_axi_sel 56
72 cko1_sel 57
73 periph 58
74 periph2 59
75 periph_clk2 60
76 periph2_clk2 61
77 ipg 62
78 ipg_per 63
79 esai_pred 64
80 esai_podf 65
81 asrc_pred 66
82 asrc_podf 67
83 spdif_pred 68
84 spdif_podf 69
85 can_root 70
86 ecspi_root 71
87 gpu2d_core_podf 72
88 gpu3d_core_podf 73
89 gpu3d_shader 74
90 ipu1_podf 75
91 ipu2_podf 76
92 ldb_di0_podf 77
93 ldb_di1_podf 78
94 ipu1_di0_pre 79
95 ipu1_di1_pre 80
96 ipu2_di0_pre 81
97 ipu2_di1_pre 82
98 hsi_tx_podf 83
99 ssi1_pred 84
100 ssi1_podf 85
101 ssi2_pred 86
102 ssi2_podf 87
103 ssi3_pred 88
104 ssi3_podf 89
105 uart_serial_podf 90
106 usdhc1_podf 91
107 usdhc2_podf 92
108 usdhc3_podf 93
109 usdhc4_podf 94
110 enfc_pred 95
111 enfc_podf 96
112 emi_podf 97
113 emi_slow_podf 98
114 vpu_axi_podf 99
115 cko1_podf 100
116 axi 101
117 mmdc_ch0_axi_podf 102
118 mmdc_ch1_axi_podf 103
119 arm 104
120 ahb 105
121 apbh_dma 106
122 asrc 107
123 can1_ipg 108
124 can1_serial 109
125 can2_ipg 110
126 can2_serial 111
127 ecspi1 112
128 ecspi2 113
129 ecspi3 114
130 ecspi4 115
131 ecspi5 116
132 enet 117
133 esai 118
134 gpt_ipg 119
135 gpt_ipg_per 120
136 gpu2d_core 121
137 gpu3d_core 122
138 hdmi_iahb 123
139 hdmi_isfr 124
140 i2c1 125
141 i2c2 126
142 i2c3 127
143 iim 128
144 enfc 129
145 ipu1 130
146 ipu1_di0 131
147 ipu1_di1 132
148 ipu2 133
149 ipu2_di0 134
150 ldb_di0 135
151 ldb_di1 136
152 ipu2_di1 137
153 hsi_tx 138
154 mlb 139
155 mmdc_ch0_axi 140
156 mmdc_ch1_axi 141
157 ocram 142
158 openvg_axi 143
159 pcie_axi 144
160 pwm1 145
161 pwm2 146
162 pwm3 147
163 pwm4 148
164 per1_bch 149
165 gpmi_bch_apb 150
166 gpmi_bch 151
167 gpmi_io 152
168 gpmi_apb 153
169 sata 154
170 sdma 155
171 spba 156
172 ssi1 157
173 ssi2 158
174 ssi3 159
175 uart_ipg 160
176 uart_serial 161
177 usboh3 162
178 usdhc1 163
179 usdhc2 164
180 usdhc3 165
181 usdhc4 166
182 vdo_axi 167
183 vpu_axi 168
184 cko1 169
185 pll1_sys 170
186 pll2_bus 171
187 pll3_usb_otg 172
188 pll4_audio 173
189 pll5_video 174
190 pll6_mlb 175
191 pll7_usb_host 176
192 pll8_enet 177
193 ssi1_ipg 178
194 ssi2_ipg 179
195 ssi3_ipg 180
196 rom 181
197 usbphy1 182
198 usbphy2 183
199 ldb_di0_div_3_5 184
200 ldb_di1_div_3_5 185
201
202Examples:
203
204clks: ccm@020c4000 {
205 compatible = "fsl,imx6q-ccm";
206 reg = <0x020c4000 0x4000>;
207 interrupts = <0 87 0x04 0 88 0x04>;
208 #clock-cells = <1>;
209 clock-output-names = ...
210 "uart_ipg",
211 "uart_serial",
212 ...;
213};
214
215uart1: serial@02020000 {
216 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
217 reg = <0x02020000 0x4000>;
218 interrupts = <0 26 0x04>;
219 clocks = <&clks 160>, <&clks 161>;
220 clock-names = "ipg", "per";
221 status = "disabled";
222};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 1c57e19e8a8a..0fb29ca7a9e1 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -122,6 +122,7 @@
122 codec: sgtl5000@0a { 122 codec: sgtl5000@0a {
123 compatible = "fsl,sgtl5000"; 123 compatible = "fsl,sgtl5000";
124 reg = <0x0a>; 124 reg = <0x0a>;
125 clocks = <&clks 169>;
125 VDDA-supply = <&reg_2p5v>; 126 VDDA-supply = <&reg_2p5v>;
126 VDDIO-supply = <&reg_3p3v>; 127 VDDIO-supply = <&reg_3p3v>;
127 }; 128 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 1d07be2530b5..e45476dc6d32 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -97,18 +97,23 @@
97 dma-apbh@00110000 { 97 dma-apbh@00110000 {
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>; 99 reg = <0x00110000 0x2000>;
100 clocks = <&clks 106>;
100 }; 101 };
101 102
102 gpmi-nand@00112000 { 103 gpmi-nand@00112000 {
103 compatible = "fsl,imx6q-gpmi-nand"; 104 compatible = "fsl,imx6q-gpmi-nand";
104 #address-cells = <1>; 105 #address-cells = <1>;
105 #size-cells = <1>; 106 #size-cells = <1>;
106 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
107 reg-names = "gpmi-nand", "bch"; 108 reg-names = "gpmi-nand", "bch";
108 interrupts = <0 13 0x04>, <0 15 0x04>; 109 interrupts = <0 13 0x04>, <0 15 0x04>;
109 interrupt-names = "gpmi-dma", "bch"; 110 interrupt-names = "gpmi-dma", "bch";
110 fsl,gpmi-dma-channel = <0>; 111 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
111 status = "disabled"; 112 <&clks 150>, <&clks 149>;
113 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
114 "gpmi_bch_apb", "per1_bch";
115 fsl,gpmi-dma-channel = <0>;
116 status = "disabled";
112 }; 117 };
113 118
114 timer@00a00600 { 119 timer@00a00600 {
@@ -150,6 +155,8 @@
150 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
151 reg = <0x02008000 0x4000>; 156 reg = <0x02008000 0x4000>;
152 interrupts = <0 31 0x04>; 157 interrupts = <0 31 0x04>;
158 clocks = <&clks 112>, <&clks 112>;
159 clock-names = "ipg", "per";
153 status = "disabled"; 160 status = "disabled";
154 }; 161 };
155 162
@@ -159,6 +166,8 @@
159 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
160 reg = <0x0200c000 0x4000>; 167 reg = <0x0200c000 0x4000>;
161 interrupts = <0 32 0x04>; 168 interrupts = <0 32 0x04>;
169 clocks = <&clks 113>, <&clks 113>;
170 clock-names = "ipg", "per";
162 status = "disabled"; 171 status = "disabled";
163 }; 172 };
164 173
@@ -168,6 +177,8 @@
168 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>; 178 reg = <0x02010000 0x4000>;
170 interrupts = <0 33 0x04>; 179 interrupts = <0 33 0x04>;
180 clocks = <&clks 114>, <&clks 114>;
181 clock-names = "ipg", "per";
171 status = "disabled"; 182 status = "disabled";
172 }; 183 };
173 184
@@ -177,6 +188,8 @@
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02014000 0x4000>; 189 reg = <0x02014000 0x4000>;
179 interrupts = <0 34 0x04>; 190 interrupts = <0 34 0x04>;
191 clocks = <&clks 115>, <&clks 115>;
192 clock-names = "ipg", "per";
180 status = "disabled"; 193 status = "disabled";
181 }; 194 };
182 195
@@ -186,6 +199,8 @@
186 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
187 reg = <0x02018000 0x4000>; 200 reg = <0x02018000 0x4000>;
188 interrupts = <0 35 0x04>; 201 interrupts = <0 35 0x04>;
202 clocks = <&clks 116>, <&clks 116>;
203 clock-names = "ipg", "per";
189 status = "disabled"; 204 status = "disabled";
190 }; 205 };
191 206
@@ -193,6 +208,8 @@
193 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 208 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
194 reg = <0x02020000 0x4000>; 209 reg = <0x02020000 0x4000>;
195 interrupts = <0 26 0x04>; 210 interrupts = <0 26 0x04>;
211 clocks = <&clks 160>, <&clks 161>;
212 clock-names = "ipg", "per";
196 status = "disabled"; 213 status = "disabled";
197 }; 214 };
198 215
@@ -205,6 +222,7 @@
205 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 222 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
206 reg = <0x02028000 0x4000>; 223 reg = <0x02028000 0x4000>;
207 interrupts = <0 46 0x04>; 224 interrupts = <0 46 0x04>;
225 clocks = <&clks 178>;
208 fsl,fifo-depth = <15>; 226 fsl,fifo-depth = <15>;
209 fsl,ssi-dma-events = <38 37>; 227 fsl,ssi-dma-events = <38 37>;
210 status = "disabled"; 228 status = "disabled";
@@ -214,6 +232,7 @@
214 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
215 reg = <0x0202c000 0x4000>; 233 reg = <0x0202c000 0x4000>;
216 interrupts = <0 47 0x04>; 234 interrupts = <0 47 0x04>;
235 clocks = <&clks 179>;
217 fsl,fifo-depth = <15>; 236 fsl,fifo-depth = <15>;
218 fsl,ssi-dma-events = <42 41>; 237 fsl,ssi-dma-events = <42 41>;
219 status = "disabled"; 238 status = "disabled";
@@ -223,6 +242,7 @@
223 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 242 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
224 reg = <0x02030000 0x4000>; 243 reg = <0x02030000 0x4000>;
225 interrupts = <0 48 0x04>; 244 interrupts = <0 48 0x04>;
245 clocks = <&clks 180>;
226 fsl,fifo-depth = <15>; 246 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <46 45>; 247 fsl,ssi-dma-events = <46 45>;
228 status = "disabled"; 248 status = "disabled";
@@ -362,19 +382,22 @@
362 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 382 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
363 reg = <0x020bc000 0x4000>; 383 reg = <0x020bc000 0x4000>;
364 interrupts = <0 80 0x04>; 384 interrupts = <0 80 0x04>;
385 clocks = <&clks 0>;
365 }; 386 };
366 387
367 wdog@020c0000 { /* WDOG2 */ 388 wdog@020c0000 { /* WDOG2 */
368 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 389 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
369 reg = <0x020c0000 0x4000>; 390 reg = <0x020c0000 0x4000>;
370 interrupts = <0 81 0x04>; 391 interrupts = <0 81 0x04>;
392 clocks = <&clks 0>;
371 status = "disabled"; 393 status = "disabled";
372 }; 394 };
373 395
374 ccm@020c4000 { 396 clks: ccm@020c4000 {
375 compatible = "fsl,imx6q-ccm"; 397 compatible = "fsl,imx6q-ccm";
376 reg = <0x020c4000 0x4000>; 398 reg = <0x020c4000 0x4000>;
377 interrupts = <0 87 0x04 0 88 0x04>; 399 interrupts = <0 87 0x04 0 88 0x04>;
400 #clock-cells = <1>;
378 }; 401 };
379 402
380 anatop@020c8000 { 403 anatop@020c8000 {
@@ -471,12 +494,14 @@
471 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 494 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
472 reg = <0x020c9000 0x1000>; 495 reg = <0x020c9000 0x1000>;
473 interrupts = <0 44 0x04>; 496 interrupts = <0 44 0x04>;
497 clocks = <&clks 182>;
474 }; 498 };
475 499
476 usbphy2: usbphy@020ca000 { 500 usbphy2: usbphy@020ca000 {
477 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 501 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
478 reg = <0x020ca000 0x1000>; 502 reg = <0x020ca000 0x1000>;
479 interrupts = <0 45 0x04>; 503 interrupts = <0 45 0x04>;
504 clocks = <&clks 183>;
480 }; 505 };
481 506
482 snvs@020cc000 { 507 snvs@020cc000 {
@@ -724,6 +749,9 @@
724 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 749 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
725 reg = <0x020ec000 0x4000>; 750 reg = <0x020ec000 0x4000>;
726 interrupts = <0 2 0x04>; 751 interrupts = <0 2 0x04>;
752 clocks = <&clks 155>, <&clks 155>;
753 clock-names = "ipg", "ahb";
754 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
727 }; 755 };
728 }; 756 };
729 757
@@ -747,6 +775,7 @@
747 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 775 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
748 reg = <0x02184000 0x200>; 776 reg = <0x02184000 0x200>;
749 interrupts = <0 43 0x04>; 777 interrupts = <0 43 0x04>;
778 clocks = <&clks 162>;
750 fsl,usbphy = <&usbphy1>; 779 fsl,usbphy = <&usbphy1>;
751 status = "disabled"; 780 status = "disabled";
752 }; 781 };
@@ -755,6 +784,7 @@
755 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 784 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
756 reg = <0x02184200 0x200>; 785 reg = <0x02184200 0x200>;
757 interrupts = <0 40 0x04>; 786 interrupts = <0 40 0x04>;
787 clocks = <&clks 162>;
758 fsl,usbphy = <&usbphy2>; 788 fsl,usbphy = <&usbphy2>;
759 status = "disabled"; 789 status = "disabled";
760 }; 790 };
@@ -763,6 +793,7 @@
763 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 793 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
764 reg = <0x02184400 0x200>; 794 reg = <0x02184400 0x200>;
765 interrupts = <0 41 0x04>; 795 interrupts = <0 41 0x04>;
796 clocks = <&clks 162>;
766 status = "disabled"; 797 status = "disabled";
767 }; 798 };
768 799
@@ -770,6 +801,7 @@
770 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 801 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
771 reg = <0x02184600 0x200>; 802 reg = <0x02184600 0x200>;
772 interrupts = <0 42 0x04>; 803 interrupts = <0 42 0x04>;
804 clocks = <&clks 162>;
773 status = "disabled"; 805 status = "disabled";
774 }; 806 };
775 807
@@ -777,6 +809,8 @@
777 compatible = "fsl,imx6q-fec"; 809 compatible = "fsl,imx6q-fec";
778 reg = <0x02188000 0x4000>; 810 reg = <0x02188000 0x4000>;
779 interrupts = <0 118 0x04 0 119 0x04>; 811 interrupts = <0 118 0x04 0 119 0x04>;
812 clocks = <&clks 117>, <&clks 117>;
813 clock-names = "ipg", "ahb";
780 status = "disabled"; 814 status = "disabled";
781 }; 815 };
782 816
@@ -789,6 +823,8 @@
789 compatible = "fsl,imx6q-usdhc"; 823 compatible = "fsl,imx6q-usdhc";
790 reg = <0x02190000 0x4000>; 824 reg = <0x02190000 0x4000>;
791 interrupts = <0 22 0x04>; 825 interrupts = <0 22 0x04>;
826 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
827 clock-names = "ipg", "ahb", "per";
792 status = "disabled"; 828 status = "disabled";
793 }; 829 };
794 830
@@ -796,6 +832,8 @@
796 compatible = "fsl,imx6q-usdhc"; 832 compatible = "fsl,imx6q-usdhc";
797 reg = <0x02194000 0x4000>; 833 reg = <0x02194000 0x4000>;
798 interrupts = <0 23 0x04>; 834 interrupts = <0 23 0x04>;
835 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
836 clock-names = "ipg", "ahb", "per";
799 status = "disabled"; 837 status = "disabled";
800 }; 838 };
801 839
@@ -803,6 +841,8 @@
803 compatible = "fsl,imx6q-usdhc"; 841 compatible = "fsl,imx6q-usdhc";
804 reg = <0x02198000 0x4000>; 842 reg = <0x02198000 0x4000>;
805 interrupts = <0 24 0x04>; 843 interrupts = <0 24 0x04>;
844 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
845 clock-names = "ipg", "ahb", "per";
806 status = "disabled"; 846 status = "disabled";
807 }; 847 };
808 848
@@ -810,6 +850,8 @@
810 compatible = "fsl,imx6q-usdhc"; 850 compatible = "fsl,imx6q-usdhc";
811 reg = <0x0219c000 0x4000>; 851 reg = <0x0219c000 0x4000>;
812 interrupts = <0 25 0x04>; 852 interrupts = <0 25 0x04>;
853 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
854 clock-names = "ipg", "ahb", "per";
813 status = "disabled"; 855 status = "disabled";
814 }; 856 };
815 857
@@ -819,6 +861,7 @@
819 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 861 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
820 reg = <0x021a0000 0x4000>; 862 reg = <0x021a0000 0x4000>;
821 interrupts = <0 36 0x04>; 863 interrupts = <0 36 0x04>;
864 clocks = <&clks 125>;
822 status = "disabled"; 865 status = "disabled";
823 }; 866 };
824 867
@@ -828,6 +871,7 @@
828 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 871 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
829 reg = <0x021a4000 0x4000>; 872 reg = <0x021a4000 0x4000>;
830 interrupts = <0 37 0x04>; 873 interrupts = <0 37 0x04>;
874 clocks = <&clks 126>;
831 status = "disabled"; 875 status = "disabled";
832 }; 876 };
833 877
@@ -837,6 +881,7 @@
837 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; 881 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
838 reg = <0x021a8000 0x4000>; 882 reg = <0x021a8000 0x4000>;
839 interrupts = <0 38 0x04>; 883 interrupts = <0 38 0x04>;
884 clocks = <&clks 127>;
840 status = "disabled"; 885 status = "disabled";
841 }; 886 };
842 887
@@ -900,6 +945,8 @@
900 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 945 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
901 reg = <0x021e8000 0x4000>; 946 reg = <0x021e8000 0x4000>;
902 interrupts = <0 27 0x04>; 947 interrupts = <0 27 0x04>;
948 clocks = <&clks 160>, <&clks 161>;
949 clock-names = "ipg", "per";
903 status = "disabled"; 950 status = "disabled";
904 }; 951 };
905 952
@@ -907,6 +954,8 @@
907 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 954 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
908 reg = <0x021ec000 0x4000>; 955 reg = <0x021ec000 0x4000>;
909 interrupts = <0 28 0x04>; 956 interrupts = <0 28 0x04>;
957 clocks = <&clks 160>, <&clks 161>;
958 clock-names = "ipg", "per";
910 status = "disabled"; 959 status = "disabled";
911 }; 960 };
912 961
@@ -914,6 +963,8 @@
914 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 963 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
915 reg = <0x021f0000 0x4000>; 964 reg = <0x021f0000 0x4000>;
916 interrupts = <0 29 0x04>; 965 interrupts = <0 29 0x04>;
966 clocks = <&clks 160>, <&clks 161>;
967 clock-names = "ipg", "per";
917 status = "disabled"; 968 status = "disabled";
918 }; 969 };
919 970
@@ -921,6 +972,8 @@
921 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 972 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
922 reg = <0x021f4000 0x4000>; 973 reg = <0x021f4000 0x4000>;
923 interrupts = <0 30 0x04>; 974 interrupts = <0 30 0x04>;
975 clocks = <&clks 160>, <&clks 161>;
976 clock-names = "ipg", "per";
924 status = "disabled"; 977 status = "disabled";
925 }; 978 };
926 }; 979 };
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ea89520b6e22..bbc71f57b92b 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -157,6 +157,7 @@ enum mx6q_clks {
157}; 157};
158 158
159static struct clk *clk[clk_max]; 159static struct clk *clk[clk_max];
160static struct clk_onecell_data clk_data;
160 161
161static enum mx6q_clks const clks_init_on[] __initconst = { 162static enum mx6q_clks const clks_init_on[] __initconst = {
162 mmdc_ch0_axi, rom, 163 mmdc_ch0_axi, rom,
@@ -392,48 +393,13 @@ int __init mx6q_clocks_init(void)
392 pr_err("i.MX6q clk %d: register failed with %ld\n", 393 pr_err("i.MX6q clk %d: register failed with %ld\n",
393 i, PTR_ERR(clk[i])); 394 i, PTR_ERR(clk[i]));
394 395
396 clk_data.clks = clk;
397 clk_data.clk_num = ARRAY_SIZE(clk);
398 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
399
395 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); 400 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
396 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 401 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
397 clk_register_clkdev(clk[twd], NULL, "smp_twd"); 402 clk_register_clkdev(clk[twd], NULL, "smp_twd");
398 clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
399 clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
400 clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
401 clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
402 clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
403 clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
404 clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
405 clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
406 clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
407 clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
408 clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
409 clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
410 clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
411 clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
412 clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
413 clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
414 clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
415 clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
416 clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
417 clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
418 clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
419 clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
420 clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
421 clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
422 clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
423 clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
424 clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
425 clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
426 clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
427 clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
428 clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
429 clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
430 clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
431 clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
432 clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
433 clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
434 clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
435 clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
436 clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
437 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); 403 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
438 clk_register_clkdev(clk[ahb], "ahb", NULL); 404 clk_register_clkdev(clk[ahb], "ahb", NULL);
439 clk_register_clkdev(clk[cko1], "cko1", NULL); 405 clk_register_clkdev(clk[cko1], "cko1", NULL);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 263bc9148183..715029ec7abf 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -99,7 +99,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
99 clk_set_parent(cko1_sel, ahb); 99 clk_set_parent(cko1_sel, ahb);
100 rate = clk_round_rate(cko1, 16000000); 100 rate = clk_round_rate(cko1, 16000000);
101 clk_set_rate(cko1, rate); 101 clk_set_rate(cko1, rate);
102 clk_register_clkdev(cko1, NULL, "0-000a");
103put_clk: 102put_clk:
104 if (!IS_ERR(cko1_sel)) 103 if (!IS_ERR(cko1_sel))
105 clk_put(cko1_sel); 104 clk_put(cko1_sel);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 09:41:30 -0400