Merge branch 'can/at91-sam9x5' of git://git.pengutronix.de/git/mkl/linux-2.6

2 files changed, 259 insertions, 112 deletions

diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 1d699e3df547..bbf06f77ee8c 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -58,9 +58,10 @@ config CAN_CALC_BITTIMING
 
 config CAN_AT91
         tristate "Atmel AT91 onchip CAN controller"
-        depends on CAN_DEV && ARCH_AT91SAM9263
+        depends on CAN_DEV && (ARCH_AT91SAM9263 || ARCH_AT91SAM9X5)
         ---help---
-          This is a driver for the SoC CAN controller in Atmel's AT91SAM9263.
+          This is a driver for the SoC CAN controller in Atmel's AT91SAM9263
+          and AT91SAM9X5 processors.
 
 config CAN_TI_HECC
         depends on CAN_DEV && ARCH_OMAP3
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index 74efb5a2ad41..121ede663e20 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -41,32 +41,7 @@
 
 #include <mach/board.h>
 
-#define AT91_NAPI_WEIGHT        11
-
-/*
- * RX/TX Mailbox split
- * don't dare to touch
- */
-#define AT91_MB_RX_NUM          11
-#define AT91_MB_TX_SHIFT        2
-
-#define AT91_MB_RX_FIRST        1
-#define AT91_MB_RX_LAST         (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
-
-#define AT91_MB_RX_MASK(i)      ((1 << (i)) - 1)
-#define AT91_MB_RX_SPLIT        8
-#define AT91_MB_RX_LOW_LAST     (AT91_MB_RX_SPLIT - 1)
-#define AT91_MB_RX_LOW_MASK     (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \
-                                 ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST))
-
-#define AT91_MB_TX_NUM          (1 << AT91_MB_TX_SHIFT)
-#define AT91_MB_TX_FIRST        (AT91_MB_RX_LAST + 1)
-#define AT91_MB_TX_LAST         (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
-
-#define AT91_NEXT_PRIO_SHIFT    (AT91_MB_TX_SHIFT)
-#define AT91_NEXT_PRIO_MASK     (0xf << AT91_MB_TX_SHIFT)
-#define AT91_NEXT_MB_MASK       (AT91_MB_TX_NUM - 1)
-#define AT91_NEXT_MASK          ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
+#define AT91_MB_MASK(i)         ((1 << (i)) - 1)
 
 /* Common registers */
 enum at91_reg {
@@ -128,12 +103,6 @@ enum at91_mb_mode {
 };
 
 /* Interrupt mask bits */
-#define AT91_IRQ_MB_RX          ((1 << (AT91_MB_RX_LAST + 1)) \
-                                 - (1 << AT91_MB_RX_FIRST))
-#define AT91_IRQ_MB_TX          ((1 << (AT91_MB_TX_LAST + 1)) \
-                                 - (1 << AT91_MB_TX_FIRST))
-#define AT91_IRQ_MB_ALL         (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
-
 #define AT91_IRQ_ERRA           (1 << 16)
 #define AT91_IRQ_WARN           (1 << 17)
 #define AT91_IRQ_ERRP           (1 << 18)
@@ -156,22 +125,51 @@ enum at91_mb_mode {
 
 #define AT91_IRQ_ALL            (0x1fffffff)
 
+enum at91_devtype {
+        AT91_DEVTYPE_SAM9263,
+        AT91_DEVTYPE_SAM9X5,
+};
+
+struct at91_devtype_data {
+        unsigned int rx_first;
+        unsigned int rx_split;
+        unsigned int rx_last;
+        unsigned int tx_shift;
+        enum at91_devtype type;
+};
+
 struct at91_priv {
-        struct can_priv         can;       /* must be the first member! */
-        struct net_device       *dev;
-        struct napi_struct      napi;
+        struct can_priv can;            /* must be the first member! */
+        struct net_device *dev;
+        struct napi_struct napi;
 
-        void __iomem            *reg_base;
+        void __iomem *reg_base;
 
-        u32                     reg_sr;
-        unsigned int            tx_next;
-        unsigned int            tx_echo;
-        unsigned int            rx_next;
+        u32 reg_sr;
+        unsigned int tx_next;
+        unsigned int tx_echo;
+        unsigned int rx_next;
+        struct at91_devtype_data devtype_data;
 
-        struct clk              *clk;
-        struct at91_can_data    *pdata;
+        struct clk *clk;
+        struct at91_can_data *pdata;
 
-        canid_t                 mb0_id;
+        canid_t mb0_id;
+};
+
+static const struct at91_devtype_data at91_devtype_data[] __devinitconst = {
+        [AT91_DEVTYPE_SAM9263] = {
+                .rx_first = 1,
+                .rx_split = 8,
+                .rx_last = 11,
+                .tx_shift = 2,
+        },
+        [AT91_DEVTYPE_SAM9X5] = {
+                .rx_first = 0,
+                .rx_split = 4,
+                .rx_last = 5,
+                .tx_shift = 1,
+        },
 };
 
 static struct can_bittiming_const at91_bittiming_const = {
@@ -186,19 +184,111 @@ static struct can_bittiming_const at91_bittiming_const = {
         .brp_inc        = 1,
 };
 
-static inline int get_tx_next_mb(const struct at91_priv *priv)
+#define AT91_IS(_model) \
+static inline int at91_is_sam##_model(const struct at91_priv *priv) \
+{ \
+        return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
+}
+
+AT91_IS(9263);
+AT91_IS(9X5);
+
+static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
+{
+        return priv->devtype_data.rx_first;
+}
+
+static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
+{
+        return priv->devtype_data.rx_last;
+}
+
+static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
+{
+        return priv->devtype_data.rx_split;
+}
+
+static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
+{
+        return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
+}
+
+static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
+{
+        return get_mb_rx_split(priv) - 1;
+}
+
+static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
+{
+        return AT91_MB_MASK(get_mb_rx_split(priv)) &
+                ~AT91_MB_MASK(get_mb_rx_first(priv));
+}
+
+static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
+{
+        return priv->devtype_data.tx_shift;
+}
+
+static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
+{
+        return 1 << get_mb_tx_shift(priv);
+}
+
+static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
+{
+        return get_mb_rx_last(priv) + 1;
+}
+
+static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)