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authorRajendra Nayak <rnayak@ti.com>2012-11-06 17:41:08 -0500
committerPaul Walmsley <paul@pwsan.com>2012-11-12 21:10:20 -0500
commitcb26867ee24a7e32ab72ec28e43456c7571c059a (patch)
treeaaa2d1e32d51014b2a5b7ed32602be8f5178b490
parent8c725dcd2246e8500a6fdd394ef4cb0cf96f2217 (diff)
ARM: OMAP4: clock: Add 44xx data using common struct clk
This patch is output from updated omap hw data autogeneration scripts mostly contributed by Mike Turquette, with some later fixes from me. All data is added into a new cclock44xx_data.c file which will be switched with clock44xx_data.c file in a later patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: replace omap2_init_clksel_parent() with omap2_clksel_find_parent_index(); reflowed macros; updated DEFINE_STRUCT_CLK_HW_OMAP macro to include clkdm_name; use macros for clksel mux+gate clocks; many other fixes] [mturquette@ti.com: converted DPLL outputs to HSDIVIDER macro; trace_clk_div_ck has clkdm ops] Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: fixed the omap-gpmc.fck alias per commit a2e5b90b; fixed several checkpatch issues; moved the dpll3xxx.c clockdomain modifications to another patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c1987
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c8
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c22
-rw-r--r--arch/arm/mach-omap2/scrm44xx.h2
5 files changed, 2013 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
new file mode 100644
index 000000000000..aa56c3e5bb34
--- /dev/null
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -0,0 +1,1987 @@
1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Mike Turquette (mturquette@ti.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * XXX Some of the ES1 clocks have been removed/changed; once support
17 * is added for discriminating clocks by ES level, these should be added back
18 * in.
19 */
20
21#include <linux/kernel.h>
22#include <linux/list.h>
23#include <linux/clk-private.h>
24#include <linux/clkdev.h>
25#include <linux/io.h>
26
27#include "soc.h"
28#include "iomap.h"
29#include "clock.h"
30#include "clock44xx.h"
31#include "cm1_44xx.h"
32#include "cm2_44xx.h"
33#include "cm-regbits-44xx.h"
34#include "prm44xx.h"
35#include "prm-regbits-44xx.h"
36#include "control.h"
37#include "scrm44xx.h"
38
39/* OMAP4 modulemode control */
40#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
41#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
42
43/* Root clocks */
44
45DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
46
47DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
48
49DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
50 OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
51 0x0, NULL);
52
53DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
54
55DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
56
57DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
58
59DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
60 OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
61 0x0, NULL);
62
63DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
64
65DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
66
67DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
68
69DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
70
71DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
72
73DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
74
75DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
76
77DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
78
79static const char *sys_clkin_ck_parents[] = {
80 "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
81 "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
82 "virt_38400000_ck",
83};
84
85DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
86 OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
87 OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
88
89DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
90
91DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
92
93DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
94
95DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
96
97DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
98
99/* Module clocks and DPLL outputs */
100
101static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
102 "sys_clkin_ck", "sys_32k_ck",
103};
104
105DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
106 NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
107 OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
108
109DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
110 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
111 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
112
113/* DPLL_ABE */
114static struct dpll_data dpll_abe_dd = {
115 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
116 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
117 .clk_ref = &abe_dpll_refclk_mux_ck,
118 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
119 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
120 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
121 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
122 .mult_mask = OMAP4430_DPLL_MULT_MASK,
123 .div1_mask = OMAP4430_DPLL_DIV_MASK,
124 .enable_mask = OMAP4430_DPLL_EN_MASK,
125 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
126 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
127 .max_multiplier = 2047,
128 .max_divider = 128,
129 .min_divider = 1,
130};
131
132
133static const char *dpll_abe_ck_parents[] = {
134 "abe_dpll_refclk_mux_ck",
135};
136
137static struct clk dpll_abe_ck;
138
139static const struct clk_ops dpll_abe_ck_ops = {
140 .enable = &omap3_noncore_dpll_enable,
141 .disable = &omap3_noncore_dpll_disable,
142 .recalc_rate = &omap4_dpll_regm4xen_recalc,
143 .round_rate = &omap4_dpll_regm4xen_round_rate,
144 .set_rate = &omap3_noncore_dpll_set_rate,
145 .get_parent = &omap2_init_dpll_parent,
146};
147
148static struct clk_hw_omap dpll_abe_ck_hw = {
149 .hw = {
150 .clk = &dpll_abe_ck,
151 },
152 .dpll_data = &dpll_abe_dd,
153 .ops = &clkhwops_omap3_dpll,
154};
155
156DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
157
158static const char *dpll_abe_x2_ck_parents[] = {
159 "dpll_abe_ck",
160};
161
162static struct clk dpll_abe_x2_ck;
163
164static const struct clk_ops dpll_abe_x2_ck_ops = {
165 .recalc_rate = &omap3_clkoutx2_recalc,
166};
167
168static struct clk_hw_omap dpll_abe_x2_ck_hw = {
169 .hw = {
170 .clk = &dpll_abe_x2_ck,
171 },
172 .flags = CLOCK_CLKOUTX2,
173 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
174 .ops = &clkhwops_omap4_dpllmx,
175};
176
177DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
178
179static const struct clk_ops omap_hsdivider_ops = {
180 .set_rate = &omap2_clksel_set_rate,
181 .recalc_rate = &omap2_clksel_recalc,
182 .round_rate = &omap2_clksel_round_rate,
183};
184
185DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
186 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
187 OMAP4430_DPLL_CLKOUT_DIV_MASK);
188
189DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
190 0x0, 1, 8);
191
192DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
193 OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
194 OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
195
196DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
197 OMAP4430_CM1_ABE_AESS_CLKCTRL,
198 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
199 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
200 0x0, NULL);
201
202DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
203 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
204 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
205
206static const char *core_hsd_byp_clk_mux_ck_parents[] = {
207 "sys_clkin_ck", "dpll_abe_m3x2_ck",
208};
209
210DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
211 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
212 OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
213 0x0, NULL);
214
215/* DPLL_CORE */
216static struct dpll_data dpll_core_dd = {
217 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
218 .clk_bypass = &core_hsd_byp_clk_mux_ck,
219 .clk_ref = &sys_clkin_ck,
220 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
221 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
222 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
223 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
224 .mult_mask = OMAP4430_DPLL_MULT_MASK,
225 .div1_mask = OMAP4430_DPLL_DIV_MASK,
226 .enable_mask = OMAP4430_DPLL_EN_MASK,
227 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
228 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
229 .max_multiplier = 2047,
230 .max_divider = 128,
231 .min_divider = 1,
232};
233
234
235static const char *dpll_core_ck_parents[] = {
236 "sys_clkin_ck",
237};
238
239static struct clk dpll_core_ck;
240
241static const struct clk_ops dpll_core_ck_ops = {
242 .recalc_rate = &omap3_dpll_recalc,
243 .get_parent = &omap2_init_dpll_parent,
244};
245
246static struct clk_hw_omap dpll_core_ck_hw = {
247 .hw = {
248 .clk = &dpll_core_ck,
249 },
250 .dpll_data = &dpll_core_dd,
251 .ops = &clkhwops_omap3_dpll,
252};
253
254DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
255
256static const char *dpll_core_x2_ck_parents[] = {
257 "dpll_core_ck",
258};
259
260static struct clk dpll_core_x2_ck;
261
262static struct clk_hw_omap dpll_core_x2_ck_hw = {
263 .hw = {
264 .clk = &dpll_core_x2_ck,
265 },
266};
267
268DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
269
270DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
271 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
272 OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
273
274DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
275 OMAP4430_CM_DIV_M2_DPLL_CORE,
276 OMAP4430_DPLL_CLKOUT_DIV_MASK);
277
278DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
279 2);
280
281DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
282 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
283 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
284
285DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
286 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
287 OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
288
289DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck",
290 &dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA,
291 OMAP4430_CLKSEL_0_1_MASK);
292
293DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
294 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
295 OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
296
297DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
298 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
299 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
300
301DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
302 0x0, 1, 2);
303
304DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
305 OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
306 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
307
308static const struct clk_ops dmic_fck_ops = {
309 .enable = &omap2_dflt_clk_enable,
310 .disable = &omap2_dflt_clk_disable,
311 .is_enabled = &omap2_dflt_clk_is_enabled,
312 .recalc_rate = &omap2_clksel_recalc,
313 .get_parent = &omap2_clksel_find_parent_index,
314 .set_parent = &omap2_clksel_set_parent,
315 .init = &omap2_init_clk_clkdm,
316};
317
318static const char *dpll_core_m3x2_ck_parents[] = {
319 "dpll_core_x2_ck",
320};
321
322static const struct clksel dpll_core_m3x2_div[] = {
323 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
324 { .parent = NULL },
325};
326
327/* XXX Missing round_rate, set_rate in ops */
328DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
329 OMAP4430_CM_DIV_M3_DPLL_CORE,
330 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
331 OMAP4430_CM_DIV_M3_DPLL_CORE,
332 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
333 dpll_core_m3x2_ck_parents, dmic_fck_ops);
334
335DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
336 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
337 OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
338
339static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
340 "sys_clkin_ck", "div_iva_hs_clk",
341};
342
343DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
344 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
345 OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
346
347/* DPLL_IVA */
348static struct dpll_data dpll_iva_dd = {
349 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
350 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
351 .clk_ref = &sys_clkin_ck,
352 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
353 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
354 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
355 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
356 .mult_mask = OMAP4430_DPLL_MULT_MASK,
357 .div1_mask = OMAP4430_DPLL_DIV_MASK,
358 .enable_mask = OMAP4430_DPLL_EN_MASK,
359 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
360 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
361 .max_multiplier = 2047,
362 .max_divider = 128,
363 .min_divider = 1,
364};
365
366static struct clk dpll_iva_ck;
367
368static struct clk_hw_omap dpll_iva_ck_hw = {
369 .hw = {
370 .clk = &dpll_iva_ck,
371 },
372 .dpll_data = &dpll_iva_dd,
373 .ops = &clkhwops_omap3_dpll,
374};
375
376DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
377
378static const char *dpll_iva_x2_ck_parents[] = {
379 "dpll_iva_ck",
380};
381
382static struct clk dpll_iva_x2_ck;
383
384static struct clk_hw_omap dpll_iva_x2_ck_hw = {
385 .hw = {
386 .clk = &dpll_iva_x2_ck,
387 },
388};
389
390DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
391
392DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
393 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
394 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
395
396DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
397 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
398 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
399
400/* DPLL_MPU */
401static struct dpll_data dpll_mpu_dd = {
402 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
403 .clk_bypass = &div_mpu_hs_clk,
404 .clk_ref = &sys_clkin_ck,
405 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
406 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
407 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
408 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
409 .mult_mask = OMAP4430_DPLL_MULT_MASK,
410 .div1_mask = OMAP4430_DPLL_DIV_MASK,
411 .enable_mask = OMAP4430_DPLL_EN_MASK,
412 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
413 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
414 .max_multiplier = 2047,
415 .max_divider = 128,
416 .min_divider = 1,
417};
418
419static struct clk dpll_mpu_ck;
420
421static struct clk_hw_omap dpll_mpu_ck_hw = {
422 .hw = {
423 .clk = &dpll_mpu_ck,
424 },
425 .dpll_data = &dpll_mpu_dd,
426 .ops = &clkhwops_omap3_dpll,
427};
428
429DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
430
431DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
432
433DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
434 OMAP4430_CM_DIV_M2_DPLL_MPU,
435 OMAP4430_DPLL_CLKOUT_DIV_MASK);
436
437DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
438 &dpll_abe_m3x2_ck, 0x0, 1, 2);
439
440static const char *per_hsd_byp_clk_mux_ck_parents[] = {
441 "sys_clkin_ck", "per_hs_clk_div_ck",
442};
443
444DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
445 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
446 OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
447
448/* DPLL_PER */
449static struct dpll_data dpll_per_dd = {
450 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
451 .clk_bypass = &per_hsd_byp_clk_mux_ck,
452 .clk_ref = &sys_clkin_ck,
453 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
454 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
455 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
456 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
457 .mult_mask = OMAP4430_DPLL_MULT_MASK,
458 .div1_mask = OMAP4430_DPLL_DIV_MASK,
459 .enable_mask = OMAP4430_DPLL_EN_MASK,
460 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
461 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
462 .max_multiplier = 2047,
463 .max_divider = 128,
464 .min_divider = 1,
465};
466
467
468static struct clk dpll_per_ck;
469
470static struct clk_hw_omap dpll_per_ck_hw = {
471 .hw = {
472 .clk = &dpll_per_ck,
473 },
474 .dpll_data = &dpll_per_dd,
475 .ops = &clkhwops_omap3_dpll,
476};
477
478DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
479
480DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
481 OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
482 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
483
484static const char *dpll_per_x2_ck_parents[] = {
485 "dpll_per_ck",
486};
487
488static struct clk dpll_per_x2_ck;
489
490static struct clk_hw_omap dpll_per_x2_ck_hw = {
491 .hw = {
492 .clk = &dpll_per_x2_ck,
493 },
494 .flags = CLOCK_CLKOUTX2,
495 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
496 .ops = &clkhwops_omap4_dpllmx,
497};
498
499DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
500
501DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
502 0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
503 OMAP4430_DPLL_CLKOUT_DIV_MASK);
504
505static const char *dpll_per_m3x2_ck_parents[] = {
506 "dpll_per_x2_ck",
507};
508
509static const struct clksel dpll_per_m3x2_div[] = {
510 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
511 { .parent = NULL },
512};
513
514/* XXX Missing round_rate, set_rate in ops */
515DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
516 OMAP4430_CM_DIV_M3_DPLL_PER,
517 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
518 OMAP4430_CM_DIV_M3_DPLL_PER,
519 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
520 dpll_per_m3x2_ck_parents, dmic_fck_ops);
521
522DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
523 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
524 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
525
526DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
527 0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
528 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
529
530DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
531 0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
532 OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
533
534DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
535 0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
536 OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
537
538DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
539 &dpll_abe_m3x2_ck, 0x0, 1, 3);
540
541/* DPLL_USB */
542static struct dpll_data dpll_usb_dd = {
543 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
544 .clk_bypass = &usb_hs_clk_div_ck,
545 .flags = DPLL_J_TYPE,
546 .clk_ref = &sys_clkin_ck,
547 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
548 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
549 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
550 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
551 .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
552 .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
553 .enable_mask = OMAP4430_DPLL_EN_MASK,
554 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
555 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
556 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
557 .max_multiplier = 4095,
558 .max_divider = 256,
559 .min_divider = 1,
560};
561
562static struct clk dpll_usb_ck;
563
564static struct clk_hw_omap dpll_usb_ck_hw = {
565 .hw = {
566 .clk = &dpll_usb_ck,
567 },
568 .dpll_data = &dpll_usb_dd,
569 .ops = &clkhwops_omap3_dpll,
570};
571
572DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
573
574static const char *dpll_usb_clkdcoldo_ck_parents[] = {
575 "dpll_usb_ck",
576};
577
578static struct clk dpll_usb_clkdcoldo_ck;
579
580static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
581};
582
583static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
584 .hw = {
585 .clk = &dpll_usb_clkdcoldo_ck,
586 },
587 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
588 .ops = &clkhwops_omap4_dpllmx,
589};
590
591DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
592 dpll_usb_clkdcoldo_ck_ops);
593
594DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
595 OMAP4430_CM_DIV_M2_DPLL_USB,
596 OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
597
598static const char *ducati_clk_mux_ck_parents[] = {
599 "div_core_ck", "dpll_per_m6x2_ck",
600};
601
602DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
603 OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
604 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
605
606DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
607 0x0, 1, 16);
608
609DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
610 1, 4);
611
612DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
613 0x0, 1, 8);
614
615static const struct clk_div_table func_48m_fclk_rates[] = {
616 { .div = 4, .val = 0 },
617 { .div = 8, .val = 1 },
618 { .div = 0 },
619};
620DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
621 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
622 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
623 NULL);
624
625DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
626 0x0, 1, 4);
627
628static const struct clk_div_table func_64m_fclk_rates[] = {
629 { .div = 2, .val = 0 },
630 { .div = 4, .val = 1 },
631 { .div = 0 },
632};
633DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
634 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
635 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
636 NULL);
637
638static const struct clk_div_table func_96m_fclk_rates[] = {
639 { .div = 2, .val = 0 },
640 { .div = 4, .val = 1 },
641 { .div = 0 },
642};
643DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
644 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
645 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
646 NULL);
647
648static const struct clk_div_table init_60m_fclk_rates[] = {
649 { .div = 1, .val = 0 },
650 { .div = 8, .val = 1 },
651 { .div = 0 },
652};
653DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
654 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
655 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
656 0x0, init_60m_fclk_rates, NULL);
657
658DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
659 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
660 OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
661
662DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
663 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
664 OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
665
666DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
667 0x0, 1, 16);
668
669static const char *l4_wkup_clk_mux_ck_parents[] = {
670 "sys_clkin_ck", "lp_clk_div_ck",
671};
672
673DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
674 OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
675 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
676
677static const struct clk_div_table ocp_abe_iclk_rates[] = {
678 { .div = 2, .val = 0 },
679 { .div = 1, .val = 1 },
680 { .div = 0 },
681};
682DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
683 OMAP4430_CM1_ABE_AESS_CLKCTRL,
684 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
685 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
686 0x0, ocp_abe_iclk_rates, NULL);
687
688DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
689 0x0, 1, 4);
690
691DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
692 OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
693 OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
694
695DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
696 OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
697 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
698
699static struct clk dbgclk_mux_ck;
700DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
701DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents,
702 dpll_usb_clkdcoldo_ck_ops);
703
704/* Leaf clocks controlled by modules */
705
706DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
707 OMAP4430_CM_L4SEC_AES1_CLKCTRL,
708 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
709
710DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
711 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
712 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
713
714DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
715 OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
716 0x0, NULL);
717
718DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
719 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
720 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
721
722static const struct clk_div_table div_ts_ck_rates[] = {
723 { .div = 8, .val = 0 },
724 { .div = 16, .val = 1 },
725 { .div = 32, .val = 2 },
726 { .div = 0 },
727};
728DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
729 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
730 OMAP4430_CLKSEL_24_25_SHIFT,
731 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
732 NULL);
733
734DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
735 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
736 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
737 0x0, NULL);
738
739DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
740 OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
741 OMAP4430_MODULEMODE_SWCTRL_SHIFT,
742 0x0, NULL);
743
744static const char *dmic_sync_mux_ck_parents[] = {
745 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
746};
747
748DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
749 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
750 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
751 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
752
753static const struct clksel func_dmic_abe_gfclk_sel[] = {
754 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
755 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
756 { .parent = &slimbus_clk, .rates = div_1_2_rates },
757 { .parent = NULL },
758};
759
760static const char *dmic_fck_parents[] = {
761 "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
762};
763
764/* Merged func_dmic_abe_gfclk into dmic */
765static struct clk dmic_fck;
766
767DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
768 OMAP4430_CM1_ABE_DMIC_CLKCTRL,
769 OMAP4430_CLKSEL_SOURCE_MASK,
770 OMAP4430_CM1_ABE_DMIC_CLKCTRL,
771 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
772 dmic_fck_parents, dmic_fck_ops);
773
774DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
775 OMAP4430_CM_TESLA_TESLA_CLKCTRL,
776 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
777
778DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
779 OMAP4430_CM_DSS_DSS_CLKCTRL,
780 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
781
782DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
783 OMAP4430_CM_DSS_DSS_CLKCTRL,
784 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
785
786DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
787 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
788 0x0, NULL);
789
790DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
791 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
792 0x0, NULL);
793
794DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
795 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
796 0x0, NULL);
797
798DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
799 OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
800 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
801
802DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
803 OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
804 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
805
806DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
807 OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
808 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
809
810DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
811 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
812 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
813
814DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
815 OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
816 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
817
818DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
819 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
820 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
821
822DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
823 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
824 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
825
826DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
827 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
828 0x0, NULL);
829
830DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
831 OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
832 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
833
834DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
835 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
836 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
837
838DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
839 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
840 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
841
842DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
843 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
844 0x0, NULL);
845
846DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
847 OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
848 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
849
850DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
851 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
852 0x0, NULL);
853
854DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
855 OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
856 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
857
858DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
859 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
860 0x0, NULL);
861
862DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
863 OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
864 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
865
866DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
867 OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
868 0x0, NULL);
869
870static const struct clksel sgx_clk_mux_sel[] = {
871 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
872 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
873 { .parent = NULL },
874};
875
876static const char *gpu_fck_parents[] = {
877 "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
878};
879
880/* Merged sgx_clk_mux into gpu */
881DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
882 OMAP4430_CM_GFX_GFX_CLKCTRL,
883 OMAP4430_CLKSEL_SGX_FCLK_MASK,
884 OMAP4430_CM_GFX_GFX_CLKCTRL,
885 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
886 gpu_fck_parents, dmic_fck_ops);
887
888DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
889 OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
890 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
891
892DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
893 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
894 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
895 NULL);
896
897DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
898 OMAP4430_CM_L4PER_I2C1_CLKCTRL,
899 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
900
901DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
902 OMAP4430_CM_L4PER_I2C2_CLKCTRL,
903 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
904
905DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
906 OMAP4430_CM_L4PER_I2C3_CLKCTRL,
907 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
908
909DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
910 OMAP4430_CM_L4PER_I2C4_CLKCTRL,
911 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
912
913DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
914 OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
915 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
916
917DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
918 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
919 0x0, NULL);
920
921DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
922 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
923 0x0, NULL);
924
925DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
926 OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
927 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
928
929DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
930 OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
931 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
932
933static struct clk l3_instr_ick;
934
935static const char *l3_instr_ick_parent_names[] = {
936 "l3_div_ck",
937};
938
939static const struct clk_ops l3_instr_ick_ops = {
940 .enable = &omap2_dflt_clk_enable,
941 .disable = &omap2_dflt_clk_disable,
942 .is_enabled = &omap2_dflt_clk_is_enabled,
943 .init = &omap2_init_clk_clkdm,
944};
945
946static struct clk_hw_omap l3_instr_ick_hw = {
947 .hw = {
948 .clk = &l3_instr_ick,
949 },
950 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
951 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
952 .clkdm_name = "l3_instr_clkdm",
953};
954
955DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
956
957static struct clk l3_main_3_ick;
958static struct clk_hw_omap l3_main_3_ick_hw = {
959 .hw = {
960 .clk = &l3_main_3_ick,
961 },
962 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
963 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
964 .clkdm_name = "l3_instr_clkdm",
965};
966
967DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
968
969DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
970 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
971 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
972 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
973
974static const struct clksel func_mcasp_abe_gfclk_sel[] = {
975 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
976 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
977 { .parent = &slimbus_clk, .rates = div_1_2_rates },
978 { .parent = NULL },
979};
980
981static const char *mcasp_fck_parents[] = {
982 "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
983};
984
985/* Merged func_mcasp_abe_gfclk into mcasp */
986DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel,
987 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
988 OMAP4430_CLKSEL_SOURCE_MASK,
989 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
990 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
991 mcasp_fck_parents, dmic_fck_ops);
992
993DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
994 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
995 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
996 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
997
998static const struct clksel func_mcbsp1_gfclk_sel[] = {
999 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1000 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1001 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1002 { .parent = NULL },
1003};
1004
1005static const char *mcbsp1_fck_parents[] = {
1006 "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1007};
1008
1009/* Merged func_mcbsp1_gfclk into mcbsp1 */
1010DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel,
1011 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1012 OMAP4430_CLKSEL_SOURCE_MASK,
1013 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1014 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1015 mcbsp1_fck_parents, dmic_fck_ops);
1016
1017DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1018 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1019 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1020 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1021
1022static const struct clksel func_mcbsp2_gfclk_sel[] = {
1023 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1024 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1025 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1026 { .parent = NULL },
1027};
1028
1029static const char *mcbsp2_fck_parents[] = {
1030 "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1031};
1032
1033/* Merged func_mcbsp2_gfclk into mcbsp2 */
1034DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel,
1035 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1036 OMAP4430_CLKSEL_SOURCE_MASK,
1037 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1038 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1039 mcbsp2_fck_parents, dmic_fck_ops);
1040
1041DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1042 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1043 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1044 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1045
1046static const struct clksel func_mcbsp3_gfclk_sel[] = {
1047 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1048 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1049 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1050 { .parent = NULL },
1051};
1052
1053static const char *mcbsp3_fck_parents[] = {
1054 "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1055};
1056
1057/* Merged func_mcbsp3_gfclk into mcbsp3 */
1058DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel,
1059 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1060 OMAP4430_CLKSEL_SOURCE_MASK,
1061 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1062 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1063 mcbsp3_fck_parents, dmic_fck_ops);
1064
1065static const char *mcbsp4_sync_mux_ck_parents[] = {
1066 "func_96m_fclk", "per_abe_nc_fclk",
1067};
1068
1069DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
1070 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1071 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1072 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1073
1074static const struct clksel per_mcbsp4_gfclk_sel[] = {
1075 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1076 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1077 { .parent = NULL },
1078};
1079
1080static const char *mcbsp4_fck_parents[] = {
1081 "mcbsp4_sync_mux_ck", "pad_clks_ck",
1082};
1083
1084/* Merged per_mcbsp4_gfclk into mcbsp4 */
1085DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1086 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1087 OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1088 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1089 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1090 mcbsp4_fck_parents, dmic_fck_ops);
1091
1092DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
1093 OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1094 0x0, NULL);
1095
1096DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1097 OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1098 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1099
1100DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1101 OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1102 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1103
1104DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1105 OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1106 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1107
1108DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1109 OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1110 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1111
1112static const struct clksel hsmmc1_fclk_sel[] = {
1113 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1114 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1115 { .parent = NULL },
1116};
1117
1118static const char *mmc1_fck_parents[] = {
1119 "func_64m_fclk", "func_96m_fclk",
1120};
1121
1122/* Merged hsmmc1_fclk into mmc1 */
1123DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1124 OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1125 OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1126 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1127 mmc1_fck_parents, dmic_fck_ops);
1128
1129/* Merged hsmmc2_fclk into mmc2 */
1130DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1131 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1132 OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
1133 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1134 mmc1_fck_parents, dmic_fck_ops);
1135
1136DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1137 OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
1138 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1139
1140DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1141 OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
1142 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1143
1144DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1145 OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
1146 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1147
1148DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1149 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1150 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1151
1152DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
1153 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1154 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1155
1156static struct clk ocp_wp_noc_ick;
1157
1158static struct clk_hw_omap ocp_wp_noc_ick_hw = {
1159 .hw = {
1160 .clk = &ocp_wp_noc_ick,
1161 },
1162 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
1163 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1164 .clkdm_name = "l3_instr_clkdm",
1165};
1166
1167DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1168
1169DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
1170 OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1171 0x0, NULL);
1172
1173DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1174 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1175 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1176
1177DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
1178 OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1179 0x0, NULL);
1180
1181DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1182 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1183 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
1184
1185DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
1186 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1187 OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
1188
1189DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
1190 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1191 OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
1192
1193DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1194 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1195 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1196
1197DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
1198 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1199 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1200
1201DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1202 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1203 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
1204
1205DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
1206 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1207 OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
1208
1209DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1210 &pad_slimbus_core_clks_ck, 0x0,
1211 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1212 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1213
1214DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
1215 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1216 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1217
1218DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1219 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1220 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1221
1222DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1223 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1224 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1225
1226DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1227 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1228 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1229
1230static const struct clksel dmt1_clk_mux_sel[] = {
1231 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1232 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1233 { .parent = NULL },
1234};
1235
1236/* Merged dmt1_clk_mux into timer1 */
1237DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1238 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1239 OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1240 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1241 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1242
1243/* Merged cm2_dm10_mux into timer10 */
1244DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1245 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1246 OMAP4430_CLKSEL_MASK,
1247 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1248 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1249 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1250
1251/* Merged cm2_dm11_mux into timer11 */
1252DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1253 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1254 OMAP4430_CLKSEL_MASK,
1255 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1256 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1257 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1258
1259/* Merged cm2_dm2_mux into timer2 */
1260DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1261 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1262 OMAP4430_CLKSEL_MASK,
1263 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1264 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1265 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1266
1267/* Merged cm2_dm3_mux into timer3 */
1268DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1269 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1270 OMAP4430_CLKSEL_MASK,
1271 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1272 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1273 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1274
1275/* Merged cm2_dm4_mux into timer4 */
1276DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1277 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1278 OMAP4430_CLKSEL_MASK,
1279 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1280 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1281 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1282
1283static const struct clksel timer5_sync_mux_sel[] = {
1284 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1285 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1286 { .parent = NULL },
1287};
1288
1289static const char *timer5_fck_parents[] = {
1290 "syc_clk_div_ck", "sys_32k_ck",
1291};
1292
1293/* Merged timer5_sync_mux into timer5 */
1294DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel,
1295 OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1296 OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1297 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1298 timer5_fck_parents, dmic_fck_ops);
1299
1300/* Merged timer6_sync_mux into timer6 */
1301DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
1302 OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1303 OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1304 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1305 timer5_fck_parents, dmic_fck_ops);
1306
1307/* Merged timer7_sync_mux into timer7 */
1308DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
1309 OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1310 OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1311 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1312 timer5_fck_parents, dmic_fck_ops);
1313
1314/* Merged timer8_sync_mux into timer8 */
1315DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
1316 OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1317 OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1318 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1319 timer5_fck_parents, dmic_fck_ops);
1320
1321/* Merged cm2_dm9_mux into timer9 */
1322DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1323 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1324 OMAP4430_CLKSEL_MASK,
1325 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1326 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1327 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1328
1329DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1330 OMAP4430_CM_L4PER_UART1_CLKCTRL,
1331 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1332
1333DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1334 OMAP4430_CM_L4PER_UART2_CLKCTRL,
1335 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1336
1337DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1338 OMAP4430_CM_L4PER_UART3_CLKCTRL,
1339 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1340
1341DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1342 OMAP4430_CM_L4PER_UART4_CLKCTRL,
1343 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1344
1345static struct clk usb_host_fs_fck;
1346
1347static const char *usb_host_fs_fck_parent_names[] = {
1348 "func_48mc_fclk",
1349};
1350
1351static const struct clk_ops usb_host_fs_fck_ops = {
1352 .enable = &omap2_dflt_clk_enable,
1353 .disable = &omap2_dflt_clk_disable,
1354 .is_enabled = &omap2_dflt_clk_is_enabled,
1355};
1356
1357static struct clk_hw_omap usb_host_fs_fck_hw = {
1358 .hw = {
1359 .clk = &usb_host_fs_fck,
1360 },
1361 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
1362 .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1363 .clkdm_name = "l3_init_clkdm",
1364};
1365
1366DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
1367 usb_host_fs_fck_ops);
1368
1369static const char *utmi_p1_gfclk_parents[] = {
1370 "init_60m_fclk", "xclk60mhsp1_ck",
1371};
1372
1373DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
1374 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1375 OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
1376 0x0, NULL);
1377
1378DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
1379 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1380 OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
1381
1382static const char *utmi_p2_gfclk_parents[] = {
1383 "init_60m_fclk", "xclk60mhsp2_ck",
1384};
1385
1386DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
1387 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1388 OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
1389 0x0, NULL);
1390
1391DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
1392 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1393 OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
1394
1395DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1396 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1397 OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
1398
1399DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
1400 &dpll_usb_m2_ck, 0x0,
1401 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1402 OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
1403
1404DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
1405 &init_60m_fclk, 0x0,
1406 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1407 OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
1408
1409DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
1410 &init_60m_fclk, 0x0,
1411 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1412 OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
1413
1414DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
1415 &dpll_usb_m2_ck, 0x0,
1416 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1417 OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
1418
1419DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
1420 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1421 OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
1422
1423DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
1424 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1425 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1426
1427static const char *otg_60m_gfclk_parents[] = {
1428 "utmi_phy_clkout_ck", "xclk60motg_ck",
1429};
1430
1431DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
1432 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
1433 OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
1434
1435DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
1436 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1437 OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
1438
1439DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
1440 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1441 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1442
1443DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
1444 OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
1445 OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
1446
1447DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1448 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1449 OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
1450
1451DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1452 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1453 OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
1454
1455DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1456 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1457 OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
1458
1459DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
1460 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1461 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1462
1463static const struct clk_div_table usim_ck_rates[] = {
1464 { .div = 14, .val = 0 },
1465 { .div = 18, .val = 1 },
1466 { .div = 0 },
1467};
1468DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
1469 OMAP4430_CM_WKUP_USIM_CLKCTRL,
1470 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
1471 0x0, usim_ck_rates, NULL);
1472
1473DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1474 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1475 0x0, NULL);
1476
1477DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1478 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1479 0x0, NULL);
1480
1481DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1482 OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1483 0x0, NULL);
1484
1485DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1486 OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1487 0x0, NULL);
1488
1489/* Remaining optional clocks */
1490static const char *pmd_stm_clock_mux_ck_parents[] = {
1491 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
1492};
1493
1494DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1495 OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
1496 OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
1497
1498DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1499 OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1500 OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
1501 OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
1502
1503DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
1504 &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1505 OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
1506 OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
1507 NULL);
1508
1509static const char *trace_clk_div_ck_parents[] = {
1510 "pmd_trace_clk_mux_ck",
1511};
1512
1513static const struct clksel trace_clk_div_div[] = {
1514 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
1515 { .parent = NULL },
1516};
1517
1518static struct clk trace_clk_div_ck;
1519
1520static const struct clk_ops trace_clk_div_ck_ops = {
1521 .recalc_rate = &omap2_clksel_recalc,
1522 .set_rate = &omap2_clksel_set_rate,
1523 .round_rate = &omap2_clksel_round_rate,
1524 .init = &omap2_init_clk_clkdm,
1525 .enable = &omap2_clkops_enable_clkdm,
1526 .disable = &omap2_clkops_disable_clkdm,
1527};
1528
1529static struct clk_hw_omap trace_clk_div_ck_hw = {
1530 .hw = {
1531 .clk = &trace_clk_div_ck,
1532 },
1533 .clkdm_name = "emu_sys_clkdm",
1534 .clksel = trace_clk_div_div,
1535 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1536 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
1537};
1538
1539DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
1540 trace_clk_div_ck_ops);
1541
1542/* SCRM aux clk nodes */
1543
1544static const struct clksel auxclk_src_sel[] = {
1545 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1546 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
1547 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
1548 { .parent = NULL },
1549};
1550
1551static const char *auxclk_src_ck_parents[] = {
1552 "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
1553};
1554
1555static const struct clk_ops auxclk_src_ck_ops = {
1556 .enable = &omap2_dflt_clk_enable,
1557 .disable = &omap2_dflt_clk_disable,
1558 .is_enabled = &omap2_dflt_clk_is_enabled,
1559 .recalc_rate = &omap2_clksel_recalc,
1560 .get_parent = &omap2_clksel_find_parent_index,
1561};
1562
1563DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
1564 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
1565 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
1566 auxclk_src_ck_parents, auxclk_src_ck_ops);
1567
1568DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
1569 OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1570 0x0, NULL);
1571
1572DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
1573 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
1574 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
1575 auxclk_src_ck_parents, auxclk_src_ck_ops);
1576
1577DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
1578 OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1579 0x0, NULL);
1580
1581DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
1582 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
1583 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
1584 auxclk_src_ck_parents, auxclk_src_ck_ops);
1585
1586DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
1587 OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1588 0x0, NULL);
1589
1590DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
1591 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
1592 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
1593 auxclk_src_ck_parents, auxclk_src_ck_ops);
1594
1595DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
1596 OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1597 0x0, NULL);
1598
1599DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
1600 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
1601 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
1602 auxclk_src_ck_parents, auxclk_src_ck_ops);
1603
1604DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
1605 OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1606 0x0, NULL);
1607
1608DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
1609 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
1610 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
1611 auxclk_src_ck_parents, auxclk_src_ck_ops);
1612
1613DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
1614 OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1615 0x0, NULL);
1616
1617static const char *auxclkreq_ck_parents[] = {
1618 "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
1619 "auxclk5_ck",
1620};
1621
1622DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
1623 OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1624 0x0, NULL);
1625
1626DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
1627 OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1628 0x0, NULL);
1629
1630DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
1631 OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1632 0x0, NULL);
1633
1634DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
1635 OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1636 0x0, NULL);
1637
1638DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
1639 OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1640 0x0, NULL);
1641
1642DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1643 OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1644 0x0, NULL);
1645
1646/*
1647 * clkdev
1648 */
1649
1650static struct omap_clk omap44xx_clks[] = {
1651 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
1652 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X),
1653 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
1654 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
1655 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
1656 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X),
1657 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
1658 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
1659 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
1660 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
1661 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
1662 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
1663 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
1664 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
1665 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
1666 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
1667 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
1668 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
1669 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
1670 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
1671 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
1672 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
1673 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
1674 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
1675 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
1676 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
1677 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
1678 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
1679 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
1680 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
1681 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
1682 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
1683 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
1684 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
1685 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
1686 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
1687 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
1688 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
1689 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
1690 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
1691 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
1692 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
1693 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
1694 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
1695 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
1696 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
1697 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
1698 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
1699 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
1700 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
1701 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
1702 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
1703 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
1704 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
1705 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
1706 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
1707 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
1708 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
1709 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
1710 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
1711 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
1712 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
1713 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
1714 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
1715 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
1716 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
1717 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
1718 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
1719 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
1720 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
1721 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
1722 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
1723 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
1724 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
1725 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
1726 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
1727 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
1728 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
1729 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
1730 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
1731 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
1732 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
1733 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
1734 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
1735 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
1736 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
1737 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
1738 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
1739 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
1740 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
1741 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
1742 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
1743 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
1744 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
1745 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
1746 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
1747 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
1748 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
1749 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
1750 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
1751 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
1752 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
1753 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
1754 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
1755 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
1756 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
1757 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
1758 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
1759 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
1760 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
1761 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
1762 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
1763 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
1764 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
1765 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
1766 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
1767 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
1768 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
1769 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
1770 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
1771 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
1772 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
1773 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
1774 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
1775 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
1776 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
1777 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
1778 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
1779 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
1780 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
1781 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
1782 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
1783 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
1784 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
1785 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
1786 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
1787 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
1788 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
1789 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
1790 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
1791 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
1792 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
1793 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
1794 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
1795 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
1796 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
1797 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
1798 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
1799 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
1800 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
1801 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
1802 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
1803 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
1804 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
1805 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
1806 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
1807 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
1808 CLK(NULL, "rng_ick", &rng_ick, CK_443X),
1809 CLK("omap_rng", "ick", &rng_ick, CK_443X),
1810 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
1811 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
1812 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
1813 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
1814 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
1815 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
1816 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
1817 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
1818 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
1819 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
1820 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
1821 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
1822 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
1823 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
1824 CLK(NULL, "timer1_fck", &timer1_fck, CK_443X),
1825 CLK(NULL, "timer10_fck", &timer10_fck, CK_443X),
1826 CLK(NULL, "timer11_fck", &timer11_fck, CK_443X),
1827 CLK(NULL, "timer2_fck", &timer2_fck, CK_443X),
1828 CLK(NULL, "timer3_fck", &timer3_fck, CK_443X),
1829 CLK(NULL, "timer4_fck", &timer4_fck, CK_443X),
1830 CLK(NULL, "timer5_fck", &timer5_fck, CK_443X),
1831 CLK(NULL, "timer6_fck", &timer6_fck, CK_443X),
1832 CLK(NULL, "timer7_fck", &timer7_fck, CK_443X),
1833 CLK(NULL, "timer8_fck", &timer8_fck, CK_443X),
1834 CLK(NULL, "timer9_fck", &timer9_fck, CK_443X),
1835 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
1836 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
1837 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
1838 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
1839 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
1840 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
1841 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
1842 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
1843 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
1844 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
1845 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
1846 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
1847 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
1848 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
1849 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
1850 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
1851 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
1852 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
1853 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
1854 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
1855 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
1856 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
1857 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
1858 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
1859 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
1860 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
1861 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
1862 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
1863 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
1864 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
1865 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
1866 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
1867 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
1868 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
1869 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
1870 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
1871 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
1872 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
1873 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
1874 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
1875 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
1876 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
1877 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
1878 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
1879 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
1880 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
1881 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
1882 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
1883 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
1884 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
1885 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
1886 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
1887 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
1888 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
1889 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
1890 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
1891 CLK("omap-gpmc", "fck", &dummy_ck, CK_443X),
1892 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
1893 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
1894 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
1895 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
1896 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
1897 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
1898 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
1899 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
1900 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
1901 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
1902 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
1903 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
1904 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
1905 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
1906 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
1907 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
1908 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
1909 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
1910 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
1911 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
1912 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
1913 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
1914 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
1915 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
1916 CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
1917 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
1918 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
1919 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
1920 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1921 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1922 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1923 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1924 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1925 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1926 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1927 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1928 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1929 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1930 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1931 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1932 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1933 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1934 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1935 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1936 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1937 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
1938 CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1939 CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1940 CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1941 CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
1942 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
1943};
1944
1945static const char *enable_init_clks[] = {
1946 "emif1_fck",
1947 "emif2_fck",
1948 "gpmc_ick",
1949 "l3_instr_ick",
1950 "l3_main_3_ick",
1951 "ocp_wp_noc_ick",
1952};
1953
1954int __init omap4xxx_clk_init(void)
1955{
1956 u32 cpu_clkflg;
1957 struct omap_clk *c;
1958
1959 if (cpu_is_omap443x()) {
1960 cpu_mask = RATE_IN_4430;
1961 cpu_clkflg = CK_443X;
1962 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1963 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
1964 cpu_clkflg = CK_446X | CK_443X;
1965
1966 if (cpu_is_omap447x())
1967 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1968 } else {
1969 return 0;
1970 }
1971
1972 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
1973 c++) {
1974 if (c->cpu & cpu_clkflg) {
1975 clkdev_add(&c->lk);
1976 if (!__clk_init(NULL, c->lk.clk))
1977 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1978 }
1979 }
1980
1981 omap2_clk_disable_autoidle_all();
1982
1983 omap2_clk_enable_init_clocks(enable_init_clks,
1984 ARRAY_SIZE(enable_init_clks));
1985
1986 return 0;
1987}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index ec63f015e60e..e1aa9c50d02f 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -641,6 +641,7 @@ extern const struct clksel_rate gpt_32k_rates[];
641extern const struct clksel_rate gpt_sys_rates[]; 641extern const struct clksel_rate gpt_sys_rates[];
642extern const struct clksel_rate gfx_l3_rates[]; 642extern const struct clksel_rate gfx_l3_rates[];
643extern const struct clksel_rate dsp_ick_rates[]; 643extern const struct clksel_rate dsp_ick_rates[];
644extern struct clk dummy_ck;
644 645
645#ifdef CONFIG_COMMON_CLK 646#ifdef CONFIG_COMMON_CLK
646extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 647extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
@@ -673,6 +674,7 @@ extern const struct clkops clkops_omap4_dpllmx_ops;
673 674
674/* clksel_rate blocks shared between OMAP44xx and AM33xx */ 675/* clksel_rate blocks shared between OMAP44xx and AM33xx */
675extern const struct clksel_rate div_1_0_rates[]; 676extern const struct clksel_rate div_1_0_rates[];
677extern const struct clksel_rate div3_1to4_rates[];
676extern const struct clksel_rate div_1_1_rates[]; 678extern const struct clksel_rate div_1_1_rates[];
677extern const struct clksel_rate div_1_2_rates[]; 679extern const struct clksel_rate div_1_2_rates[];
678extern const struct clksel_rate div_1_3_rates[]; 680extern const struct clksel_rate div_1_3_rates[];
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2a450c9b9a7b..ef6d09e9a938 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -275,13 +275,6 @@ static struct clk abe_24m_fclk = {
275 .recalc = &omap_fixed_divisor_recalc, 275 .recalc = &omap_fixed_divisor_recalc,
276}; 276};
277 277
278static const struct clksel_rate div3_1to4_rates[] = {
279 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
280 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
281 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
282 { .div = 0 },
283};
284
285static const struct clksel abe_clk_div[] = { 278static const struct clksel abe_clk_div[] = {
286 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, 279 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
287 { .parent = NULL }, 280 { .parent = NULL },
@@ -677,7 +670,6 @@ static struct dpll_data dpll_mpu_dd = {
677 .min_divider = 1, 670 .min_divider = 1,
678}; 671};
679 672
680
681static struct clk dpll_mpu_ck = { 673static struct clk dpll_mpu_ck = {
682 .name = "dpll_mpu_ck", 674 .name = "dpll_mpu_ck",
683 .parent = &sys_clkin_ck, 675 .parent = &sys_clkin_ck,
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index b9f3ba68148c..c0d02a97b768 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -52,6 +52,13 @@ const struct clksel_rate div_1_0_rates[] = {
52 { .div = 0 }, 52 { .div = 0 },
53}; 53};
54 54
55const struct clksel_rate div3_1to4_rates[] = {
56 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
57 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
58 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
59 { .div = 0 },
60};
61
55const struct clksel_rate div_1_1_rates[] = { 62const struct clksel_rate div_1_1_rates[] = {
56 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, 63 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
57 { .div = 0 }, 64 { .div = 0 },
@@ -108,6 +115,19 @@ const struct clksel_rate div31_1to31_rates[] = {
108}; 115};
109 116
110/* Clocks shared between various OMAP SoCs */ 117/* Clocks shared between various OMAP SoCs */
118#ifdef CONFIG_COMMON_CLK
119
120#include <linux/clk-private.h>
121
122static struct clk_ops dummy_ck_ops = {};
123
124struct clk dummy_ck = {
125 .name = "dummy_clk",
126 .ops = &dummy_ck_ops,
127 .flags = CLK_IS_BASIC,
128};
129
130#else
111 131
112struct clk virt_19200000_ck = { 132struct clk virt_19200000_ck = {
113 .name = "virt_19200000_ck", 133 .name = "virt_19200000_ck",
@@ -120,3 +140,5 @@ struct clk virt_26000000_ck = {
120 .ops = &clkops_null, 140 .ops = &clkops_null,
121 .rate = 26000000, 141 .rate = 26000000,
122}; 142};
143
144#endif
diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h
index 701bf2d32949..e897ac89a3fd 100644
--- a/arch/arm/mach-omap2/scrm44xx.h
+++ b/arch/arm/mach-omap2/scrm44xx.h
@@ -127,12 +127,14 @@
127/* AUXCLKREQ0 */ 127/* AUXCLKREQ0 */
128#define OMAP4_MAPPING_SHIFT 2 128#define OMAP4_MAPPING_SHIFT 2
129#define OMAP4_MAPPING_MASK (0x7 << 2) 129#define OMAP4_MAPPING_MASK (0x7 << 2)
130#define OMAP4_MAPPING_WIDTH 3
130#define OMAP4_ACCURACY_SHIFT 1 131#define OMAP4_ACCURACY_SHIFT 1
131#define OMAP4_ACCURACY_MASK (1 << 1) 132#define OMAP4_ACCURACY_MASK (1 << 1)
132 133
133/* AUXCLK0 */ 134/* AUXCLK0 */
134#define OMAP4_CLKDIV_SHIFT 16 135#define OMAP4_CLKDIV_SHIFT 16
135#define OMAP4_CLKDIV_MASK (0xf << 16) 136#define OMAP4_CLKDIV_MASK (0xf << 16)
137#define OMAP4_CLKDIV_WIDTH 4
136#define OMAP4_DISABLECLK_SHIFT 9 138#define OMAP4_DISABLECLK_SHIFT 9
137#define OMAP4_DISABLECLK_MASK (1 << 9) 139#define OMAP4_DISABLECLK_MASK (1 << 9)
138#define OMAP4_ENABLE_SHIFT 8 140#define OMAP4_ENABLE_SHIFT 8
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 06:06:08 -0500