ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod

OCMC RAM lies in the PER power domain and this memory
support retention.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

1 files changed, 27 insertions, 20 deletions

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 646c14d9fdb9..8280f1162e68 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -414,7 +414,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  *    - cEFUSE (doesn't fall under any ocp_if)
  *    - clkdiv32k
  *    - debugss
- *    - ocmc ram
  *    - ocp watch point
  *    - aes0
  *    - sha0
@@ -481,25 +480,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
         },
 };
 
-/* ocmcram */
-static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
-        .name = "ocmcram",
-};
-
-static struct omap_hwmod am33xx_ocmcram_hwmod = {
-        .name           = "ocmcram",
-        .class          = &am33xx_ocmcram_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
 /* ocpwp */
 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
         .name           = "ocpwp",
@@ -570,6 +550,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
 
 #endif
 
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+        .name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+        .name           = "ocmcram",
+        .class          = &am33xx_ocmcram_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
 /* 'smartreflex' class */
 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
         .name           = "smartreflex",
@@ -3328,6 +3327,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
         .flags          = OCPIF_SWSUP_IDLE,
 };
 
+/* l3 main -> ocmc */
+static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_ocmcram_hwmod,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_fw__emif_fw,
         &am33xx_l3_main__emif,
@@ -3398,6 +3404,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l3_main__tptc0,
         &am33xx_l3_main__tptc1,
         &am33xx_l3_main__tptc2,
+        &am33xx_l3_main__ocmc,
         &am33xx_l3_s__usbss,
         &am33xx_l4_hs__cpgmac0,
         &am33xx_cpgmac0__mdio,