drm/tegra: sor - Change power down ordering

Lanes are powered up in decreasing order. Power them down in increasing
order for consistency.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 735c76babdf2..f082ea22f32e 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -748,7 +748,7 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 
         /* stop lane sequencer */
-        value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
+        value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);