x86/mce: Reindent __mcheck_cpu_apply_quirks() properly

Had some strange 3 tabs + 2 chars indentation, probably from me. Fix it.

No code changed:

  # arch/x86/kernel/cpu/mcheck/mce.o:

   text    data     bss     dec     hex filename
  21371    5923     264   27558    6ba6 mce.o.before
  21371    5923     264   27558    6ba6 mce.o.after

md5:
   eb3996c84d15e08ed836f043df2cbb01  mce.o.before.asm
   eb3996c84d15e08ed836f043df2cbb01  mce.o.after.asm

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 24 insertions, 24 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 196a1e34fe39..8548b714a16b 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1531,39 +1531,39 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
                  * Various K7s with broken bank 0 around. Always disable
                  * by default.
                  */
-                 if (c->x86 == 6 && cfg->banks > 0)
+                if (c->x86 == 6 && cfg->banks > 0)
                         mce_banks[0].ctl = 0;
 
-                 /*
-                  * Turn off MC4_MISC thresholding banks on those models since
-                  * they're not supported there.
-                  */
-                 if (c->x86 == 0x15 &&
-                     (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
-                         int i;
-                         u64 hwcr;
-                         bool need_toggle;
-                         u32 msrs[] = {
+                /*
+                 * Turn off MC4_MISC thresholding banks on those models since
+                 * they're not supported there.
+                 */
+                if (c->x86 == 0x15 &&
+                    (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
+                        int i;
+                        u64 hwcr;
+                        bool need_toggle;
+                        u32 msrs[] = {
                                 0x00000413, /* MC4_MISC0 */
                                 0xc0000408, /* MC4_MISC1 */
-                         };
+                        };
 
-                         rdmsrl(MSR_K7_HWCR, hwcr);
+                        rdmsrl(MSR_K7_HWCR, hwcr);
 
-                         /* McStatusWrEn has to be set */
-                         need_toggle = !(hwcr & BIT(18));
+                        /* McStatusWrEn has to be set */
+                        need_toggle = !(hwcr & BIT(18));
 
-                         if (need_toggle)
-                                 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
+                        if (need_toggle)
+                                wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
 
-                         /* Clear CntP bit safely */
-                         for (i = 0; i < ARRAY_SIZE(msrs); i++)
-                                 msr_clear_bit(msrs[i], 62);
+                        /* Clear CntP bit safely */
+                        for (i = 0; i < ARRAY_SIZE(msrs); i++)
+                                msr_clear_bit(msrs[i], 62);
 
-                         /* restore old settings */
-                         if (need_toggle)
-                                 wrmsrl(MSR_K7_HWCR, hwcr);
-                 }
+                        /* restore old settings */
+                        if (need_toggle)
+                                wrmsrl(MSR_K7_HWCR, hwcr);
+                }
         }
 
         if (c->x86_vendor == X86_VENDOR_INTEL) {