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authorAaro Koskinen <aaro.koskinen@iki.fi>2011-02-13 17:11:27 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-03-22 02:20:45 -0400
commitc9982d59c5c877a65fbdef3c875e82eaa95c2505 (patch)
tree19d4149c9b9d23013d8757c086124f32bc632159
parent5e8700bf6db24ccf6814c765519d8986f1c16357 (diff)
sisfb: move XGI POST DDR2 bootup code into subroutines
Move DDR2 register setting code into separate subroutines. No changes in functionality. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Thomas Winischhofer <thomas@winischhofer.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--drivers/video/sis/sis_main.c139
1 files changed, 84 insertions, 55 deletions
diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c
index de0356788375..9c52d7bbef70 100644
--- a/drivers/video/sis/sis_main.c
+++ b/drivers/video/sis/sis_main.c
@@ -4941,6 +4941,89 @@ sisfb_post_xgi_setclocks(struct sis_video_info *ivideo, u8 regb)
4941 sisfb_post_xgi_delay(ivideo, 0x43); 4941 sisfb_post_xgi_delay(ivideo, 0x43);
4942} 4942}
4943 4943
4944static void __devinit
4945sisfb_post_xgi_ddr2_mrs_default(struct sis_video_info *ivideo, u8 regb)
4946{
4947 unsigned char *bios = ivideo->bios_abase;
4948 u8 v1;
4949
4950 SiS_SetReg(SISSR, 0x28, 0x64);
4951 SiS_SetReg(SISSR, 0x29, 0x63);
4952 sisfb_post_xgi_delay(ivideo, 15);
4953 SiS_SetReg(SISSR, 0x18, 0x00);
4954 SiS_SetReg(SISSR, 0x19, 0x20);
4955 SiS_SetReg(SISSR, 0x16, 0x00);
4956 SiS_SetReg(SISSR, 0x16, 0x80);
4957 SiS_SetReg(SISSR, 0x18, 0xc5);
4958 SiS_SetReg(SISSR, 0x19, 0x23);
4959 SiS_SetReg(SISSR, 0x16, 0x00);
4960 SiS_SetReg(SISSR, 0x16, 0x80);
4961 sisfb_post_xgi_delay(ivideo, 1);
4962 SiS_SetReg(SISCR, 0x97, 0x11);
4963 sisfb_post_xgi_setclocks(ivideo, regb);
4964 sisfb_post_xgi_delay(ivideo, 0x46);
4965 SiS_SetReg(SISSR, 0x18, 0xc5);
4966 SiS_SetReg(SISSR, 0x19, 0x23);
4967 SiS_SetReg(SISSR, 0x16, 0x00);
4968 SiS_SetReg(SISSR, 0x16, 0x80);
4969 sisfb_post_xgi_delay(ivideo, 1);
4970 SiS_SetReg(SISSR, 0x1b, 0x04);
4971 sisfb_post_xgi_delay(ivideo, 1);
4972 SiS_SetReg(SISSR, 0x1b, 0x00);
4973 sisfb_post_xgi_delay(ivideo, 1);
4974 v1 = 0x31;
4975 if (ivideo->haveXGIROM) {
4976 v1 = bios[0xf0];
4977 }
4978 SiS_SetReg(SISSR, 0x18, v1);
4979 SiS_SetReg(SISSR, 0x19, 0x06);
4980 SiS_SetReg(SISSR, 0x16, 0x04);
4981 SiS_SetReg(SISSR, 0x16, 0x84);
4982 sisfb_post_xgi_delay(ivideo, 1);
4983}
4984
4985static void __devinit
4986sisfb_post_xgi_ddr2(struct sis_video_info *ivideo, u8 regb)
4987{
4988 unsigned char *bios = ivideo->bios_abase;
4989 static const u8 cs158[8] = {
4990 0x88, 0xaa, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00
4991 };
4992 static const u8 cs160[8] = {
4993 0x44, 0x77, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00
4994 };
4995 static const u8 cs168[8] = {
4996 0x48, 0x78, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00
4997 };
4998 u8 reg;
4999 u8 v1;
5000 u8 v2;
5001 u8 v3;
5002
5003 SiS_SetReg(SISCR, 0x82, 0x77);
5004 SiS_SetReg(SISCR, 0x86, 0x00);
5005 reg = SiS_GetReg(SISCR, 0x86);
5006 SiS_SetReg(SISCR, 0x86, 0x88);
5007 reg = SiS_GetReg(SISCR, 0x86);
5008 v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
5009 if (ivideo->haveXGIROM) {
5010 v1 = bios[regb + 0x168];
5011 v2 = bios[regb + 0x160];
5012 v3 = bios[regb + 0x158];
5013 }
5014 SiS_SetReg(SISCR, 0x86, v1);
5015 SiS_SetReg(SISCR, 0x82, 0x77);
5016 SiS_SetReg(SISCR, 0x85, 0x00);
5017 reg = SiS_GetReg(SISCR, 0x85);
5018 SiS_SetReg(SISCR, 0x85, 0x88);
5019 reg = SiS_GetReg(SISCR, 0x85);
5020 SiS_SetReg(SISCR, 0x85, v2);
5021 SiS_SetReg(SISCR, 0x82, v3);
5022 SiS_SetReg(SISCR, 0x98, 0x01);
5023 SiS_SetReg(SISCR, 0x9a, 0x02);
5024 sisfb_post_xgi_ddr2_default(ivideo, regb);
5025}
5026
4944static u8 __devinit 5027static u8 __devinit
4945sisfb_post_xgi_ramtype(struct sis_video_info *ivideo) 5028sisfb_post_xgi_ramtype(struct sis_video_info *ivideo)
4946{ 5029{
@@ -5514,61 +5597,7 @@ sisfb_post_xgi(struct pci_dev *pdev)
5514 SiS_SetReg(SISSR, 0x1b, 0x00); 5597 SiS_SetReg(SISSR, 0x1b, 0x00);
5515 break; 5598 break;
5516 case 1: 5599 case 1:
5517 SiS_SetReg(SISCR, 0x82, 0x77); 5600 sisfb_post_xgi_ddr2(ivideo, regb);
5518 SiS_SetReg(SISCR, 0x86, 0x00);
5519 reg = SiS_GetReg(SISCR, 0x86);
5520 SiS_SetReg(SISCR, 0x86, 0x88);
5521 reg = SiS_GetReg(SISCR, 0x86);
5522 v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
5523 if(ivideo->haveXGIROM) {
5524 v1 = bios[regb + 0x168];
5525 v2 = bios[regb + 0x160];
5526 v3 = bios[regb + 0x158];
5527 }
5528 SiS_SetReg(SISCR, 0x86, v1);
5529 SiS_SetReg(SISCR, 0x82, 0x77);
5530 SiS_SetReg(SISCR, 0x85, 0x00);
5531 reg = SiS_GetReg(SISCR, 0x85);
5532 SiS_SetReg(SISCR, 0x85, 0x88);
5533 reg = SiS_GetReg(SISCR, 0x85);
5534 SiS_SetReg(SISCR, 0x85, v2);
5535 SiS_SetReg(SISCR, 0x82, v3);
5536 SiS_SetReg(SISCR, 0x98, 0x01);
5537 SiS_SetReg(SISCR, 0x9a, 0x02);
5538
5539 SiS_SetReg(SISSR, 0x28, 0x64);
5540 SiS_SetReg(SISSR, 0x29, 0x63);
5541 sisfb_post_xgi_delay(ivideo, 15);
5542 SiS_SetReg(SISSR, 0x18, 0x00);
5543 SiS_SetReg(SISSR, 0x19, 0x20);
5544 SiS_SetReg(SISSR, 0x16, 0x00);
5545 SiS_SetReg(SISSR, 0x16, 0x80);
5546 SiS_SetReg(SISSR, 0x18, 0xc5);
5547 SiS_SetReg(SISSR, 0x19, 0x23);
5548 SiS_SetReg(SISSR, 0x16, 0x00);
5549 SiS_SetReg(SISSR, 0x16, 0x80);
5550 sisfb_post_xgi_delay(ivideo, 1);
5551 SiS_SetReg(SISCR, 0x97, 0x11);
5552 sisfb_post_xgi_setclocks(ivideo, regb);
5553 sisfb_post_xgi_delay(ivideo, 0x46);
5554 SiS_SetReg(SISSR, 0x18, 0xc5);
5555 SiS_SetReg(SISSR, 0x19, 0x23);
5556 SiS_SetReg(SISSR, 0x16, 0x00);
5557 SiS_SetReg(SISSR, 0x16, 0x80);
5558 sisfb_post_xgi_delay(ivideo, 1);
5559 SiS_SetReg(SISSR, 0x1b, 0x04);
5560 sisfb_post_xgi_delay(ivideo, 1);
5561 SiS_SetReg(SISSR, 0x1b, 0x00);
5562 sisfb_post_xgi_delay(ivideo, 1);
5563 v1 = 0x31;
5564 if(ivideo->haveXGIROM) {
5565 v1 = bios[0xf0];
5566 }
5567 SiS_SetReg(SISSR, 0x18, v1);
5568 SiS_SetReg(SISSR, 0x19, 0x06);
5569 SiS_SetReg(SISSR, 0x16, 0x04);
5570 SiS_SetReg(SISSR, 0x16, 0x84);
5571 sisfb_post_xgi_delay(ivideo, 1);
5572 break; 5601 break;
5573 default: 5602 default:
5574 sisfb_post_xgi_setclocks(ivideo, regb); 5603 sisfb_post_xgi_setclocks(ivideo, regb);