MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions

MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and
BEQZALC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

3 files changed, 21 insertions, 1 deletions

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 9ce5e34b9c64..782af0f83421 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -21,7 +21,7 @@
 enum major_op {
         spec_op, bcond_op, j_op, jal_op,
         beq_op, bne_op, blez_op, bgtz_op,
-        addi_op, addiu_op, slti_op, sltiu_op,
+        addi_op, cbcond0_op = addi_op, addiu_op, slti_op, sltiu_op,
         andi_op, ori_op, xori_op, lui_op,
         cop0_op, cop1_op, cop2_op, cop1x_op,
         beql_op, bnel_op, blezl_op, bgtzl_op,
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 1a0a30e16684..80a073ced200 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -790,6 +790,17 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                 regs->cp0_epc += 8;
                 break;
 #endif
+        case cbcond0_op:
+                /* Only valid for MIPS R6 */
+                if (!cpu_has_mips_r6) {
+                        ret = -SIGILL;
+                        break;
+                }
+                /* Compact branches: bovc, beqc, beqzalc */
+                if (insn.i_format.rt && !insn.i_format.rs)
+                        regs->regs[31] = epc + 4;
+                regs->cp0_epc += 8;
+                break;
         }
 
         return ret;
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 7f373a2858b5..c115d969664b 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -623,6 +623,15 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                                 dec_insn.pc_inc +
                                 dec_insn.next_pc_inc;
                 return 1;
+        case cbcond0_op:
+                if (!cpu_has_mips_r6)
+                        break;
+                if (insn.i_format.rt && !insn.i_format.rs)
+                        regs->regs[31] = regs->cp0_epc + 4;
+                *contpc = regs->cp0_epc + dec_insn.pc_inc +
+                        dec_insn.next_pc_inc;
+
+                return 1;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
         case lwc2_op: /* This is bbit0 on Octeon */
                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)