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authorLee Jones <lee.jones@linaro.org>2013-05-03 10:32:01 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-05-23 15:12:36 -0400
commitc86519c1ab025969e551441bb35bb8ec28f8cff0 (patch)
tree7cd85bdae2bd4202a3db2db14ef4bd6dd1ce7221
parentde63589efa7950a74949073699b26703b833d162 (diff)
ARM: ux500: Remove unused 'data_width' attributes from UART DMA configs
DMA configuration data is now allocated in the UART driver, so these are just ignored. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--arch/arm/mach-ux500/board-mop500.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index f48e88dbda15..e3dafdd713c9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -504,48 +504,36 @@ static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
504 .mode = STEDMA40_MODE_LOGICAL, 504 .mode = STEDMA40_MODE_LOGICAL,
505 .dir = STEDMA40_PERIPH_TO_MEM, 505 .dir = STEDMA40_PERIPH_TO_MEM,
506 .dev_type = DB8500_DMA_DEV13_UART0, 506 .dev_type = DB8500_DMA_DEV13_UART0,
507 .src_info.data_width = STEDMA40_BYTE_WIDTH,
508 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
509}; 507};
510 508
511static struct stedma40_chan_cfg uart0_dma_cfg_tx = { 509static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
512 .mode = STEDMA40_MODE_LOGICAL, 510 .mode = STEDMA40_MODE_LOGICAL,
513 .dir = STEDMA40_MEM_TO_PERIPH, 511 .dir = STEDMA40_MEM_TO_PERIPH,
514 .dev_type = DB8500_DMA_DEV13_UART0, 512 .dev_type = DB8500_DMA_DEV13_UART0,
515 .src_info.data_width = STEDMA40_BYTE_WIDTH,
516 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
517}; 513};
518 514
519static struct stedma40_chan_cfg uart1_dma_cfg_rx = { 515static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
520 .mode = STEDMA40_MODE_LOGICAL, 516 .mode = STEDMA40_MODE_LOGICAL,
521 .dir = STEDMA40_PERIPH_TO_MEM, 517 .dir = STEDMA40_PERIPH_TO_MEM,
522 .dev_type = DB8500_DMA_DEV12_UART1, 518 .dev_type = DB8500_DMA_DEV12_UART1,
523 .src_info.data_width = STEDMA40_BYTE_WIDTH,
524 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
525}; 519};
526 520
527static struct stedma40_chan_cfg uart1_dma_cfg_tx = { 521static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
528 .mode = STEDMA40_MODE_LOGICAL, 522 .mode = STEDMA40_MODE_LOGICAL,
529 .dir = STEDMA40_MEM_TO_PERIPH, 523 .dir = STEDMA40_MEM_TO_PERIPH,
530 .dev_type = DB8500_DMA_DEV12_UART1, 524 .dev_type = DB8500_DMA_DEV12_UART1,
531 .src_info.data_width = STEDMA40_BYTE_WIDTH,
532 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
533}; 525};
534 526
535static struct stedma40_chan_cfg uart2_dma_cfg_rx = { 527static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
536 .mode = STEDMA40_MODE_LOGICAL, 528 .mode = STEDMA40_MODE_LOGICAL,
537 .dir = STEDMA40_PERIPH_TO_MEM, 529 .dir = STEDMA40_PERIPH_TO_MEM,
538 .dev_type = DB8500_DMA_DEV11_UART2, 530 .dev_type = DB8500_DMA_DEV11_UART2,
539 .src_info.data_width = STEDMA40_BYTE_WIDTH,
540 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
541}; 531};
542 532
543static struct stedma40_chan_cfg uart2_dma_cfg_tx = { 533static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
544 .mode = STEDMA40_MODE_LOGICAL, 534 .mode = STEDMA40_MODE_LOGICAL,
545 .dir = STEDMA40_MEM_TO_PERIPH, 535 .dir = STEDMA40_MEM_TO_PERIPH,
546 .dev_type = DB8500_DMA_DEV11_UART2, 536 .dev_type = DB8500_DMA_DEV11_UART2,
547 .src_info.data_width = STEDMA40_BYTE_WIDTH,
548 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
549}; 537};
550#endif 538#endif
551 539