ARM: 8120/1: crypto: sha512: add ARM NEON implementation

This patch adds ARM NEON assembly implementation of SHA-512 and SHA-384
algorithms.

tcrypt benchmark results on Cortex-A8, sha512-generic vs sha512-neon-asm:

block-size      bytes/update    old-vs-new
16              16              2.99x
64              16              2.67x
64              64              3.00x
256             16              2.64x
256             64              3.06x
256             256             3.33x
1024            16              2.53x
1024            256             3.39x
1024            1024            3.52x
2048            16              2.50x
2048            256             3.41x
2048            1024            3.54x
2048            2048            3.57x
4096            16              2.49x
4096            256             3.42x
4096            1024            3.56x
4096            4096            3.59x
8192            16              2.48x
8192            256             3.42x
8192            1024            3.56x
8192            4096            3.60x
8192            8192            3.60x

Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

4 files changed, 777 insertions, 0 deletions

diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
index 374956d2f896..b48fa341648d 100644
--- a/arch/arm/crypto/Makefile
+++ b/arch/arm/crypto/Makefile
@@ -6,11 +6,13 @@ obj-$(CONFIG_CRYPTO_AES_ARM) += aes-arm.o
 obj-$(CONFIG_CRYPTO_AES_ARM_BS) += aes-arm-bs.o
 obj-$(CONFIG_CRYPTO_SHA1_ARM) += sha1-arm.o
 obj-$(CONFIG_CRYPTO_SHA1_ARM_NEON) += sha1-arm-neon.o
+obj-$(CONFIG_CRYPTO_SHA512_ARM_NEON) += sha512-arm-neon.o
 
 aes-arm-y       := aes-armv4.o aes_glue.o
 aes-arm-bs-y    := aesbs-core.o aesbs-glue.o
 sha1-arm-y      := sha1-armv4-large.o sha1_glue.o
 sha1-arm-neon-y := sha1-armv7-neon.o sha1_neon_glue.o
+sha512-arm-neon-y := sha512-armv7-neon.o sha512_neon_glue.o
 
 quiet_cmd_perl = PERL    $@
       cmd_perl = $(PERL) $(<) > $(@)
diff --git a/arch/arm/crypto/sha512-armv7-neon.S b/arch/arm/crypto/sha512-armv7-neon.S
new file mode 100644
index 000000000000..fe99472e507c
--- /dev/null
+++ b/arch/arm/crypto/sha512-armv7-neon.S
@@ -0,0 +1,455 @@
+/* sha512-armv7-neon.S  -  ARM/NEON assembly implementation of SHA-512 transform
+ *
+ * Copyright © 2013-2014 Jussi Kivilinna <jussi.kivilinna@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <linux/linkage.h>
+
+
+.syntax unified
+.code   32
+.fpu neon
+
+.text
+
+/* structure of SHA512_CONTEXT */
+#define hd_a 0
+#define hd_b ((hd_a) + 8)
+#define hd_c ((hd_b) + 8)
+#define hd_d ((hd_c) + 8)
+#define hd_e ((hd_d) + 8)
+#define hd_f ((hd_e) + 8)
+#define hd_g ((hd_f) + 8)
+
+/* register macros */
+#define RK %r2
+
+#define RA d0
+#define RB d1
+#define RC d2
+#define RD d3
+#define RE d4
+#define RF d5
+#define RG d6
+#define RH d7
+
+#define RT0 d8
+#define RT1 d9
+#define RT2 d10
+#define RT3 d11
+#define RT4 d12
+#define RT5 d13
+#define RT6 d14
+#define RT7 d15
+
+#define RT01q q4
+#define RT23q q5
+#define RT45q q6
+#define RT67q q7
+
+#define RW0 d16
+#define RW1 d17
+#define RW2 d18
+#define RW3 d19
+#define RW4 d20
+#define RW5 d21
+#define RW6 d22
+#define RW7 d23
+#define RW8 d24
+#define RW9 d25
+#define RW10 d26
+#define RW11 d27
+#define RW12 d28
+#define RW13 d29
+#define RW14 d30
+#define RW15 d31
+
+#define RW01q q8
+#define RW23q q9
+#define RW45q q10
+#define RW67q q11
+#define RW89q q12
+#define RW1011q q13
+#define RW1213q q14
+#define RW1415q q15
+
+/***********************************************************************
+ * ARM assembly implementation of sha512 transform
+ ***********************************************************************/
+#define rounds2_0_63(ra, rb, rc, rd, re, rf, rg, rh, rw0, rw1, rw01q, rw2, \
+                     rw23q, rw1415q, rw9, rw10, interleave_op, arg1) \
+        /* t1 = h + Sum1 (e) + Ch (e, f, g) + k[t] + w[t]; */ \
+        vshr.u64 RT2, re, #14; \
+        vshl.u64 RT3, re, #64 - 14; \
+        interleave_op(arg1); \
+        vshr.u64 RT4, re, #18; \
+        vshl.u64 RT5, re, #64 - 18; \
+        vld1.64 {RT0}, [RK]!; \
+        veor.64 RT23q, RT23q, RT45q; \
+        vshr.u64 RT4, re, #41; \
+        vshl.u64 RT5, re, #64 - 41; \
+        vadd.u64 RT0, RT0, rw0; \
+        veor.64 RT23q, RT23q, RT45q; \
+        vmov.64 RT7, re; \
+        veor.64 RT1, RT2, RT3; \
+        vbsl.64 RT7, rf, rg; \
+        \
+        vadd.u64 RT1, RT1, rh; \
+        vshr.u64 RT2, ra, #28; \
+        vshl.u64 RT3, ra, #64 - 28; \
+        vadd.u64 RT1, RT1, RT0; \
+        vshr.u64 RT4, ra, #34; \
+        vshl.u64 RT5, ra, #64 - 34; \
+        vadd.u64 RT1, RT1, RT7; \
+        \
+        /* h = Sum0 (a) + Maj (a, b, c); */ \
+        veor.64 RT23q, RT23q, RT45q; \
+        vshr.u64 RT4, ra, #39; \
+        vshl.u64 RT5, ra, #64 - 39; \
+        veor.64 RT0, ra, rb; \
+        veor.64 RT23q, RT23q, RT45q; \
+        vbsl.64 RT0, rc, rb; \
+        vadd.u64 rd, rd, RT1; /* d+=t1; */ \
+        veor.64 rh, RT2, RT3; \
+        \
+        /* t1 = g + Sum1 (d) + Ch (d, e, f) + k[t] + w[t]; */ \
+        vshr.u64 RT2, rd, #14; \
+        vshl.u64 RT3, rd, #64 - 14; \
+        vadd.u64 rh, rh, RT0; \
+        vshr.u64 RT4, rd, #18; \
+        vshl.u64 RT5, rd, #64 - 18; \
+        vadd.u64 rh, rh, RT1; /* h+=t1; */ \
+        vld1.64 {RT0}, [RK]!; \
+        veor.64 RT23q, RT23q, RT45q; \
+        vshr.u64 RT4, rd, #41; \
+        vshl.u64 RT5, rd, #64 - 41; \
+        vadd.u64 RT0, RT0, rw1; \
+        veor.64 RT23q, RT23q, RT45q; \
+        vmov.64 RT7, rd; \
+        veor.64 RT1, RT2, RT3; \
+        vbsl.64 RT7, re, rf; \
+        \
+        vadd.u64 RT1, RT1, rg; \
+        vshr.u64 RT2, rh, #28; \
+        vshl.u64 RT3, rh, #64 - 28; \
+        vadd.u64 RT1, RT1, RT0; \
+        vshr.u64 RT4, rh, #34; \
+        vshl.u64 RT5, rh, #64 - 34; \
+        vadd.u64 RT1, RT1, RT7; \
+        \
+        /* g = Sum0 (h) + Maj (h, a, b); */ \
+        veor.64 RT23q, RT23q, RT45q; \
+        vshr.u64 RT4, rh, #39; \
+        vshl.u64 RT5, rh, #64 - 39; \
+        veor.64 RT0, rh, ra; \
+        veor.64 RT23q, RT23q, RT45q; \
+        vbsl.64 RT0, rb, ra; \
+        vadd.u64 rc, rc, RT1; /* c+=t1; */ \
+        veor.64 rg, RT2, RT3; \
+        \
+        /* w[0] += S1 (w[14]) + w[9] + S0 (w[1]); */ \
+        /* w[1] += S1 (w[15]) + w[10] + S0 (w[2]); */ \
+        \
+        /**** S0(w[1:2]) */ \
+        \
+        /* w[0:1] += w[9:10] */ \
+        /* RT23q = rw1:rw2 */ \
+        vext.u64 RT23q, rw01q, rw23q, #1; \
+        vadd.u64 rw0, rw9; \
+        vadd.u64 rg, rg, RT0; \
+        vadd.u64 rw1, rw10;\
+        vadd.u64 rg, rg, RT1; /* g+=t1; */ \