drm/radeon: Add RADEON_GEM_CPU_ACCESS BO creation flag

This flag is a hint that userspace expects the BO to be accessed by the
CPU. We can use that hint to prevent such BOs from ever being stored in
the CPU inaccessible part of VRAM.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 11 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index aadbd36e64b9..eef60aaf4e64 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -144,7 +144,12 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
 
         for (i = 0; i < c; ++i) {
                 rbo->placements[i].fpfn = 0;
-                rbo->placements[i].lpfn = 0;
+                if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
+                    (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
+                        rbo->placements[i].lpfn =
+                                rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+                else
+                        rbo->placements[i].lpfn = 0;
         }
 
         /*
@@ -152,7 +157,9 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
          * improve fragmentation quality.
          * 512kb was measured as the most optimal number.
          */
-        if (rbo->tbo.mem.size > 512 * 1024) {
+        if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
+              (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) &&
+            rbo->tbo.mem.size > 512 * 1024) {
                 for (i = 0; i < c; i++) {
                         rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
                 }
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 375b6e656c54..f755f20d2b5c 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -801,6 +801,8 @@ struct drm_radeon_gem_info {
 #define RADEON_GEM_NO_BACKING_STORE     (1 << 0)
 #define RADEON_GEM_GTT_UC               (1 << 1)
 #define RADEON_GEM_GTT_WC               (1 << 2)
+/* BO is expected to be accessed by the CPU */
+#define RADEON_GEM_CPU_ACCESS           (1 << 3)
 
 struct drm_radeon_gem_create {
         uint64_t        size;