drm/i915: Remove vblank wait from haswell_write_eld

The pipe is off at that point in time, so a vblank wait is simply a
50ms wait. Caught by Jesse's verbose "make vblank wait timeouts WARN"
patch. We've probably had a few versions of this float around already.

To document assumptions put a pipe assert into the same place. And
also add a posting read.

If we ever decide to update the eld and infoframes while the pipe is
already on (e.g. for fastboot) then there's lots of work to do. So
better properly document all the hidden assumptions.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f32c7bccbec7..420070b08ac4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7336,7 +7336,6 @@ static void haswell_write_eld(struct drm_connector *connector,
 {
         struct drm_i915_private *dev_priv = connector->dev->dev_private;
         uint8_t *eld = connector->eld;
-        struct drm_device *dev = crtc->dev;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         uint32_t eldv;
         uint32_t i;
@@ -7354,9 +7353,9 @@ static void haswell_write_eld(struct drm_connector *connector,
         tmp = I915_READ(aud_cntrl_st2);
         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
         I915_WRITE(aud_cntrl_st2, tmp);
+        POSTING_READ(aud_cntrl_st2);
 
-        /* Wait for 1 vertical blank */
-        intel_wait_for_vblank(dev, pipe);
+        assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
 
         /* Set ELD valid state */
         tmp = I915_READ(aud_cntrl_st2);