mfd: max14577: Add MAX14577 prefix to IRQ defines

This patch prepares for adding support for MAX77836 device to existing
max14577 driver by adding MAX14577 prefix to defines of interrupts.

This is only a rename-like patch, new code is not added.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

2 files changed, 26 insertions, 26 deletions

diff --git a/drivers/mfd/max14577.c b/drivers/mfd/max14577.c
index 0e07ed74ab41..6f39dec9dfdf 100644
--- a/drivers/mfd/max14577.c
+++ b/drivers/mfd/max14577.c
@@ -66,20 +66,20 @@ static const struct regmap_config max14577_muic_regmap_config = {
 
 static const struct regmap_irq max14577_irqs[] = {
         /* INT1 interrupts */
-        { .reg_offset = 0, .mask = INT1_ADC_MASK, },
-        { .reg_offset = 0, .mask = INT1_ADCLOW_MASK, },
-        { .reg_offset = 0, .mask = INT1_ADCERR_MASK, },
+        { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
+        { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
+        { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
         /* INT2 interrupts */
-        { .reg_offset = 1, .mask = INT2_CHGTYP_MASK, },
-        { .reg_offset = 1, .mask = INT2_CHGDETRUN_MASK, },
-        { .reg_offset = 1, .mask = INT2_DCDTMR_MASK, },
-        { .reg_offset = 1, .mask = INT2_DBCHG_MASK, },
-        { .reg_offset = 1, .mask = INT2_VBVOLT_MASK, },
+        { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
+        { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
+        { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
+        { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
+        { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
         /* INT3 interrupts */
-        { .reg_offset = 2, .mask = INT3_EOC_MASK, },
-        { .reg_offset = 2, .mask = INT3_CGMBC_MASK, },
-        { .reg_offset = 2, .mask = INT3_OVP_MASK, },
-        { .reg_offset = 2, .mask = INT3_MBCCHGERR_MASK, },
+        { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
+        { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
+        { .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
+        { .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
 };
 
 static const struct regmap_irq_chip max14577_irq_chip = {
diff --git a/include/linux/mfd/max14577-private.h b/include/linux/mfd/max14577-private.h
index 1ce6f2952cc9..989183d232cd 100644
--- a/include/linux/mfd/max14577-private.h
+++ b/include/linux/mfd/max14577-private.h
@@ -79,20 +79,20 @@ enum max14577_muic_charger_type {
 };
 
 /* MAX14577 interrupts */
-#define INT1_ADC_MASK                   (0x1 << 0)
-#define INT1_ADCLOW_MASK                (0x1 << 1)
-#define INT1_ADCERR_MASK                (0x1 << 2)
-
-#define INT2_CHGTYP_MASK                (0x1 << 0)
-#define INT2_CHGDETRUN_MASK             (0x1 << 1)
-#define INT2_DCDTMR_MASK                (0x1 << 2)
-#define INT2_DBCHG_MASK                 (0x1 << 3)
-#define INT2_VBVOLT_MASK                (0x1 << 4)
-
-#define INT3_EOC_MASK                   (0x1 << 0)
-#define INT3_CGMBC_MASK                 (0x1 << 1)
-#define INT3_OVP_MASK                   (0x1 << 2)
-#define INT3_MBCCHGERR_MASK             (0x1 << 3)
+#define MAX14577_INT1_ADC_MASK          BIT(0)
+#define MAX14577_INT1_ADCLOW_MASK       BIT(1)
+#define MAX14577_INT1_ADCERR_MASK       BIT(2)
+
+#define MAX14577_INT2_CHGTYP_MASK       BIT(0)
+#define MAX14577_INT2_CHGDETRUN_MASK    BIT(1)
+#define MAX14577_INT2_DCDTMR_MASK       BIT(2)
+#define MAX14577_INT2_DBCHG_MASK        BIT(3)
+#define MAX14577_INT2_VBVOLT_MASK       BIT(4)
+
+#define MAX14577_INT3_EOC_MASK          BIT(0)
+#define MAX14577_INT3_CGMBC_MASK        BIT(1)
+#define MAX14577_INT3_OVP_MASK          BIT(2)
+#define MAX14577_INT3_MBCCHGERR_MASK    BIT(3)
 
 /* MAX14577 DEVICE ID register */
 #define DEVID_VENDORID_SHIFT            0