diff options
author | Maxime Coquelin <maxime.coquelin@st.com> | 2014-10-31 04:47:54 -0400 |
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committer | Maxime Coquelin <maxime.coquelin@st.com> | 2014-10-31 04:47:54 -0400 |
commit | c759e5f76b18350ed2417e89588d6358e58e1ad3 (patch) | |
tree | 1f4074147f050e3a66f61b7afd0457f22d4b9cb9 | |
parent | f114040e3ea6e07372334ade75d1ee0775c355e1 (diff) |
reset: stih407: Add reset controllers DT bindings
This patch adds softreset, powerdown and picophy reset controllers
DT bindings for the STiH407 SoC.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
-rw-r--r-- | include/dt-bindings/reset-controller/stih407-resets.h | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/include/dt-bindings/reset-controller/stih407-resets.h b/include/dt-bindings/reset-controller/stih407-resets.h new file mode 100644 index 000000000000..02d4328fe479 --- /dev/null +++ b/include/dt-bindings/reset-controller/stih407-resets.h | |||
@@ -0,0 +1,61 @@ | |||
1 | /* | ||
2 | * This header provides constants for the reset controller | ||
3 | * based peripheral powerdown requests on the STMicroelectronics | ||
4 | * STiH407 SoC. | ||
5 | */ | ||
6 | #ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 | ||
7 | #define _DT_BINDINGS_RESET_CONTROLLER_STIH407 | ||
8 | |||
9 | /* Powerdown requests control 0 */ | ||
10 | #define STIH407_EMISS_POWERDOWN 0 | ||
11 | #define STIH407_NAND_POWERDOWN 1 | ||
12 | |||
13 | /* Synp GMAC PowerDown */ | ||
14 | #define STIH407_ETH1_POWERDOWN 2 | ||
15 | |||
16 | /* Powerdown requests control 1 */ | ||
17 | #define STIH407_USB3_POWERDOWN 3 | ||
18 | #define STIH407_USB2_PORT1_POWERDOWN 4 | ||
19 | #define STIH407_USB2_PORT0_POWERDOWN 5 | ||
20 | #define STIH407_PCIE1_POWERDOWN 6 | ||
21 | #define STIH407_PCIE0_POWERDOWN 7 | ||
22 | #define STIH407_SATA1_POWERDOWN 8 | ||
23 | #define STIH407_SATA0_POWERDOWN 9 | ||
24 | |||
25 | /* Reset defines */ | ||
26 | #define STIH407_ETH1_SOFTRESET 0 | ||
27 | #define STIH407_MMC1_SOFTRESET 1 | ||
28 | #define STIH407_PICOPHY_SOFTRESET 2 | ||
29 | #define STIH407_IRB_SOFTRESET 3 | ||
30 | #define STIH407_PCIE0_SOFTRESET 4 | ||
31 | #define STIH407_PCIE1_SOFTRESET 5 | ||
32 | #define STIH407_SATA0_SOFTRESET 6 | ||
33 | #define STIH407_SATA1_SOFTRESET 7 | ||
34 | #define STIH407_MIPHY0_SOFTRESET 8 | ||
35 | #define STIH407_MIPHY1_SOFTRESET 9 | ||
36 | #define STIH407_MIPHY2_SOFTRESET 10 | ||
37 | #define STIH407_SATA0_PWR_SOFTRESET 11 | ||
38 | #define STIH407_SATA1_PWR_SOFTRESET 12 | ||
39 | #define STIH407_DELTA_SOFTRESET 13 | ||
40 | #define STIH407_BLITTER_SOFTRESET 14 | ||
41 | #define STIH407_HDTVOUT_SOFTRESET 15 | ||
42 | #define STIH407_HDQVDP_SOFTRESET 16 | ||
43 | #define STIH407_VDP_AUX_SOFTRESET 17 | ||
44 | #define STIH407_COMPO_SOFTRESET 18 | ||
45 | #define STIH407_HDMI_TX_PHY_SOFTRESET 19 | ||
46 | #define STIH407_JPEG_DEC_SOFTRESET 20 | ||
47 | #define STIH407_VP8_DEC_SOFTRESET 21 | ||
48 | #define STIH407_GPU_SOFTRESET 22 | ||
49 | #define STIH407_HVA_SOFTRESET 23 | ||
50 | #define STIH407_ERAM_HVA_SOFTRESET 24 | ||
51 | #define STIH407_LPM_SOFTRESET 25 | ||
52 | #define STIH407_KEYSCAN_SOFTRESET 26 | ||
53 | #define STIH407_USB2_PORT0_SOFTRESET 27 | ||
54 | #define STIH407_USB2_PORT1_SOFTRESET 28 | ||
55 | |||
56 | /* Picophy reset defines */ | ||
57 | #define STIH407_PICOPHY0_RESET 0 | ||
58 | #define STIH407_PICOPHY1_RESET 1 | ||
59 | #define STIH407_PICOPHY2_RESET 2 | ||
60 | |||
61 | #endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ | ||