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author | Stefan Brüns <stefan.bruens@rwth-aachen.de> | 2014-07-12 19:47:14 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-08-05 08:53:27 -0400 |
commit | c748990b7b1c320c626c758379d50748588c6ed6 (patch) | |
tree | 98d02d254187d332e5494b21ec825741b05985bc | |
parent | 59bc1d89d6a4d67c94a9b70fa81bda1d5b04f0cb (diff) |
drm/radeon: Use correct value for unknown audio/video latency
Valid values are 1 to 251 for 0 to 500 ms latency, 0 for unknown
and 255 for audio/video unsupported by sink, according to HDMI 1.3 spec.
Also matches Radeon HDA verb 0xf7b documentation.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/dce6_afmt.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c index 0a65dc7e93e7..af936cc09b61 100644 --- a/drivers/gpu/drm/radeon/dce6_afmt.c +++ b/drivers/gpu/drm/radeon/dce6_afmt.c | |||
@@ -136,13 +136,13 @@ void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, | |||
136 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | | 136 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
137 | AUDIO_LIPSYNC(connector->audio_latency[1]); | 137 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
138 | else | 138 | else |
139 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); | 139 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
140 | } else { | 140 | } else { |
141 | if (connector->latency_present[0]) | 141 | if (connector->latency_present[0]) |
142 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | | 142 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
143 | AUDIO_LIPSYNC(connector->audio_latency[0]); | 143 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
144 | else | 144 | else |
145 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); | 145 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
146 | } | 146 | } |
147 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); | 147 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); |
148 | } | 148 | } |