diff options
author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2013-12-03 08:57:18 -0500 |
---|---|---|
committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2013-12-16 08:37:45 -0500 |
commit | c63badebfebacdba827ab1cc1d420fc81bd8d818 (patch) | |
tree | 6bc09659dd889c7d85b09e7d1283cfecf08859a8 | |
parent | 1c182a628075af7431edb8155601740867b5ae51 (diff) |
s390: optimize control register update
It is less expensive to update control registers 0 and 2 with two
individual stctg/lctlg instructions as with a single one that spans
control register 0, 1 and 2.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
-rw-r--r-- | arch/s390/kernel/ptrace.c | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index c369a26d1d56..f6be6087a0e9 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c | |||
@@ -56,25 +56,26 @@ void update_cr_regs(struct task_struct *task) | |||
56 | #ifdef CONFIG_64BIT | 56 | #ifdef CONFIG_64BIT |
57 | /* Take care of the enable/disable of transactional execution. */ | 57 | /* Take care of the enable/disable of transactional execution. */ |
58 | if (MACHINE_HAS_TE) { | 58 | if (MACHINE_HAS_TE) { |
59 | unsigned long cr[3], cr_new[3]; | 59 | unsigned long cr, cr_new; |
60 | 60 | ||
61 | __ctl_store(cr, 0, 2); | 61 | __ctl_store(cr, 0, 0); |
62 | cr_new[1] = cr[1]; | ||
63 | /* Set or clear transaction execution TXC bit 8. */ | 62 | /* Set or clear transaction execution TXC bit 8. */ |
63 | cr_new = cr | (1UL << 55); | ||
64 | if (task->thread.per_flags & PER_FLAG_NO_TE) | 64 | if (task->thread.per_flags & PER_FLAG_NO_TE) |
65 | cr_new[0] = cr[0] & ~(1UL << 55); | 65 | cr_new &= ~(1UL << 55); |
66 | else | 66 | if (cr_new != cr) |
67 | cr_new[0] = cr[0] | (1UL << 55); | 67 | __ctl_load(cr, 0, 0); |
68 | /* Set or clear transaction execution TDC bits 62 and 63. */ | 68 | /* Set or clear transaction execution TDC bits 62 and 63. */ |
69 | cr_new[2] = cr[2] & ~3UL; | 69 | __ctl_store(cr, 2, 2); |
70 | cr_new = cr & ~3UL; | ||
70 | if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND) { | 71 | if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND) { |
71 | if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND_TEND) | 72 | if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND_TEND) |
72 | cr_new[2] |= 1UL; | 73 | cr_new |= 1UL; |
73 | else | 74 | else |
74 | cr_new[2] |= 2UL; | 75 | cr_new |= 2UL; |
75 | } | 76 | } |
76 | if (memcmp(&cr_new, &cr, sizeof(cr))) | 77 | if (cr_new != cr) |
77 | __ctl_load(cr_new, 0, 2); | 78 | __ctl_load(cr_new, 2, 2); |
78 | } | 79 | } |
79 | #endif | 80 | #endif |
80 | /* Copy user specified PER registers */ | 81 | /* Copy user specified PER registers */ |