crypto: crypto4xx - Perform read/modify/write on device control register

The Security function on the AMCC SoCs has multiple engines within a
single MMIO range.  The crypto driver currently enables the 3DES
functionality by doing a blind write to the device control register.
This can unintentionally disable other functions like the PKA or TRNG
when the driver is loaded.

Perform a read/modify/write to enable the 3DES function instead.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

1 files changed, 4 insertions, 1 deletions

diff --git a/drivers/crypto/amcc/crypto4xx_core.c b/drivers/crypto/amcc/crypto4xx_core.c
index 18912521a7a5..1d103f997dc2 100644
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -51,6 +51,7 @@ static void crypto4xx_hw_init(struct crypto4xx_device *dev)
         union ce_io_threshold io_threshold;
         u32 rand_num;
         union ce_pe_dma_cfg pe_dma_cfg;
+        u32 device_ctrl;
 
         writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
         /* setup pe dma, include reset sg, pdr and pe, then release reset */
@@ -84,7 +85,9 @@ static void crypto4xx_hw_init(struct crypto4xx_device *dev)
         writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
         ring_ctrl.w = 0;
         writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
-        writel(PPC4XX_DC_3DES_EN, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
+        device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
+        device_ctrl |= PPC4XX_DC_3DES_EN;
+        writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
         writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
         writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
         part_ring_size.w = 0;