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authorEmilio López <emilio@elopez.com.ar>2013-12-22 22:32:38 -0500
committerEmilio López <emilio@elopez.com.ar>2013-12-28 15:28:23 -0500
commitc3e5e66b65a57df8025cbf59801d9c357cf807ea (patch)
tree7c9310308b86b8f87050538768b9a0a060029a5c
parentec5589f7a33956ea3671d198ff170dc51ff2145d (diff)
ARM: sunxi: add PLL5 and PLL6 support
This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi19
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi19
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi19
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi28
4 files changed, 67 insertions, 18 deletions
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index a6c1caeae6a0..5e2fc45f3c1a 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -73,6 +73,22 @@
73 clocks = <&osc24M>; 73 clocks = <&osc24M>;
74 }; 74 };
75 75
76 pll5: pll5@01c20020 {
77 #clock-cells = <1>;
78 compatible = "allwinner,sun4i-pll5-clk";
79 reg = <0x01c20020 0x4>;
80 clocks = <&osc24M>;
81 clock-output-names = "pll5_ddr", "pll5_other";
82 };
83
84 pll6: pll6@01c20028 {
85 #clock-cells = <1>;
86 compatible = "allwinner,sun4i-pll6-clk";
87 reg = <0x01c20028 0x4>;
88 clocks = <&osc24M>;
89 clock-output-names = "pll6_sata", "pll6_other", "pll6";
90 };
91
76 /* dummy is 200M */ 92 /* dummy is 200M */
77 cpu: cpu@01c20054 { 93 cpu: cpu@01c20054 {
78 #clock-cells = <0>; 94 #clock-cells = <0>;
@@ -138,12 +154,11 @@
138 "apb0_ir1", "apb0_keypad"; 154 "apb0_ir1", "apb0_keypad";
139 }; 155 };
140 156
141 /* dummy is pll62 */
142 apb1_mux: apb1_mux@01c20058 { 157 apb1_mux: apb1_mux@01c20058 {
143 #clock-cells = <0>; 158 #clock-cells = <0>;
144 compatible = "allwinner,sun4i-apb1-mux-clk"; 159 compatible = "allwinner,sun4i-apb1-mux-clk";
145 reg = <0x01c20058 0x4>; 160 reg = <0x01c20058 0x4>;
146 clocks = <&osc24M>, <&dummy>, <&osc32k>; 161 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
147 }; 162 };
148 163
149 apb1: apb1@01c20058 { 164 apb1: apb1@01c20058 {
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index c3f4eed3691b..b29412ac98df 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -70,6 +70,22 @@
70 clocks = <&osc24M>; 70 clocks = <&osc24M>;
71 }; 71 };
72 72
73 pll5: pll5@01c20020 {
74 #clock-cells = <1>;
75 compatible = "allwinner,sun4i-pll5-clk";
76 reg = <0x01c20020 0x4>;
77 clocks = <&osc24M>;
78 clock-output-names = "pll5_ddr", "pll5_other";
79 };
80
81 pll6: pll6@01c20028 {
82 #clock-cells = <1>;
83 compatible = "allwinner,sun4i-pll6-clk";
84 reg = <0x01c20028 0x4>;
85 clocks = <&osc24M>;
86 clock-output-names = "pll6_sata", "pll6_other", "pll6";
87 };
88
73 /* dummy is 200M */ 89 /* dummy is 200M */
74 cpu: cpu@01c20054 { 90 cpu: cpu@01c20054 {
75 #clock-cells = <0>; 91 #clock-cells = <0>;
@@ -130,12 +146,11 @@
130 "apb0_ir", "apb0_keypad"; 146 "apb0_ir", "apb0_keypad";
131 }; 147 };
132 148
133 /* dummy is pll62 */
134 apb1_mux: apb1_mux@01c20058 { 149 apb1_mux: apb1_mux@01c20058 {
135 #clock-cells = <0>; 150 #clock-cells = <0>;
136 compatible = "allwinner,sun4i-apb1-mux-clk"; 151 compatible = "allwinner,sun4i-apb1-mux-clk";
137 reg = <0x01c20058 0x4>; 152 reg = <0x01c20058 0x4>;
138 clocks = <&osc24M>, <&dummy>, <&osc32k>; 153 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
139 }; 154 };
140 155
141 apb1: apb1@01c20058 { 156 apb1: apb1@01c20058 {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8c4a9c3c069c..cded3c796974 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -74,6 +74,22 @@
74 clocks = <&osc24M>; 74 clocks = <&osc24M>;
75 }; 75 };
76 76
77 pll5: pll5@01c20020 {
78 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk";
80 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other";
83 };
84
85 pll6: pll6@01c20028 {
86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk";
88 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6";
91 };
92
77 /* dummy is 200M */ 93 /* dummy is 200M */
78 cpu: cpu@01c20054 { 94 cpu: cpu@01c20054 {
79 #clock-cells = <0>; 95 #clock-cells = <0>;
@@ -132,12 +148,11 @@
132 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; 148 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
133 }; 149 };
134 150
135 /* dummy is pll6 */
136 apb1_mux: apb1_mux@01c20058 { 151 apb1_mux: apb1_mux@01c20058 {
137 #clock-cells = <0>; 152 #clock-cells = <0>;
138 compatible = "allwinner,sun4i-apb1-mux-clk"; 153 compatible = "allwinner,sun4i-apb1-mux-clk";
139 reg = <0x01c20058 0x4>; 154 reg = <0x01c20058 0x4>;
140 clocks = <&osc24M>, <&dummy>, <&osc32k>; 155 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
141 }; 156 };
142 157
143 apb1: apb1@01c20058 { 158 apb1: apb1@01c20058 {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e4a5d37a12f8..a6cd039d5a0c 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -69,23 +69,27 @@
69 clocks = <&osc24M>; 69 clocks = <&osc24M>;
70 }; 70 };
71 71
72 /* 72 pll5: pll5@01c20020 {
73 * This is a dummy clock, to be used as placeholder on 73 #clock-cells = <1>;
74 * other mux clocks when a specific parent clock is not 74 compatible = "allwinner,sun4i-pll5-clk";
75 * yet implemented. It should be dropped when the driver 75 reg = <0x01c20020 0x4>;
76 * is complete. 76 clocks = <&osc24M>;
77 */ 77 clock-output-names = "pll5_ddr", "pll5_other";
78 pll6: pll6 { 78 };
79 #clock-cells = <0>; 79
80 compatible = "fixed-clock"; 80 pll6: pll6@01c20028 {
81 clock-frequency = <0>; 81 #clock-cells = <1>;
82 compatible = "allwinner,sun4i-pll6-clk";
83 reg = <0x01c20028 0x4>;
84 clocks = <&osc24M>;
85 clock-output-names = "pll6_sata", "pll6_other", "pll6";
82 }; 86 };
83 87
84 cpu: cpu@01c20054 { 88 cpu: cpu@01c20054 {
85 #clock-cells = <0>; 89 #clock-cells = <0>;
86 compatible = "allwinner,sun4i-cpu-clk"; 90 compatible = "allwinner,sun4i-cpu-clk";
87 reg = <0x01c20054 0x4>; 91 reg = <0x01c20054 0x4>;
88 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>; 92 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
89 }; 93 };
90 94
91 axi: axi@01c20054 { 95 axi: axi@01c20054 {
@@ -144,7 +148,7 @@
144 #clock-cells = <0>; 148 #clock-cells = <0>;
145 compatible = "allwinner,sun4i-apb1-mux-clk"; 149 compatible = "allwinner,sun4i-apb1-mux-clk";
146 reg = <0x01c20058 0x4>; 150 reg = <0x01c20058 0x4>;
147 clocks = <&osc24M>, <&pll6>, <&osc32k>; 151 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
148 }; 152 };
149 153
150 apb1: apb1@01c20058 { 154 apb1: apb1@01c20058 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-02 00:39:35 -0400