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authorLars-Peter Clausen <lars@metafoo.de>2013-09-27 07:47:08 -0400
committerMark Brown <broonie@linaro.org>2013-09-27 09:28:40 -0400
commitc3df37c9380d70f19a9cb2de4c7d58d7822a4b35 (patch)
tree9b938fbfe22bfbbf0aae651e73c2f9f3aa0cb272
parent4a10c2ac2f368583138b774ca41fac4207911983 (diff)
ASoC: adau1373: Convert to direct regmap usage
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat
-rw-r--r--sound/soc/codecs/adau1373.c295
1 files changed, 235 insertions, 60 deletions
diff --git a/sound/soc/codecs/adau1373.c b/sound/soc/codecs/adau1373.c
index 1aa10ddf3a61..c57c1f81a611 100644
--- a/sound/soc/codecs/adau1373.c
+++ b/sound/soc/codecs/adau1373.c
@@ -32,6 +32,7 @@ struct adau1373_dai {
32}; 32};
33 33
34struct adau1373 { 34struct adau1373 {
35 struct regmap *regmap;
35 struct adau1373_dai dais[3]; 36 struct adau1373_dai dais[3];
36}; 37};
37 38
@@ -152,37 +153,172 @@ struct adau1373 {
152#define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4 153#define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
153#define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2 154#define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
154 155
155static const uint8_t adau1373_default_regs[] = { 156static const struct reg_default adau1373_reg_defaults[] = {
156 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x00 */ 157 { ADAU1373_INPUT_MODE, 0x00 },
157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 158 { ADAU1373_AINL_CTRL(0), 0x00 },
158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x10 */ 159 { ADAU1373_AINR_CTRL(0), 0x00 },
159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 160 { ADAU1373_AINL_CTRL(1), 0x00 },
160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 161 { ADAU1373_AINR_CTRL(1), 0x00 },
161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 162 { ADAU1373_AINL_CTRL(2), 0x00 },
162 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, /* 0x30 */ 163 { ADAU1373_AINR_CTRL(2), 0x00 },
163 0x00, 0x00, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 164 { ADAU1373_AINL_CTRL(3), 0x00 },
164 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x00, /* 0x40 */ 165 { ADAU1373_AINR_CTRL(3), 0x00 },
165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 166 { ADAU1373_LLINE_OUT(0), 0x00 },
166 0x00, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /* 0x50 */ 167 { ADAU1373_RLINE_OUT(0), 0x00 },
167 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 168 { ADAU1373_LLINE_OUT(1), 0x00 },
168 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60 */ 169 { ADAU1373_RLINE_OUT(1), 0x00 },
169 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 170 { ADAU1373_LSPK_OUT, 0x00 },
170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x70 */ 171 { ADAU1373_RSPK_OUT, 0x00 },
171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 172 { ADAU1373_LHP_OUT, 0x00 },
172 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0x80 */ 173 { ADAU1373_RHP_OUT, 0x00 },
173 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 174 { ADAU1373_ADC_GAIN, 0x00 },
174 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0x90 */ 175 { ADAU1373_LADC_MIXER, 0x00 },
175 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 176 { ADAU1373_RADC_MIXER, 0x00 },
176 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0xa0 */ 177 { ADAU1373_LLINE1_MIX, 0x00 },
177 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 178 { ADAU1373_RLINE1_MIX, 0x00 },
178 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */ 179 { ADAU1373_LLINE2_MIX, 0x00 },
179 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 180 { ADAU1373_RLINE2_MIX, 0x00 },
180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc0 */ 181 { ADAU1373_LSPK_MIX, 0x00 },
181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 182 { ADAU1373_RSPK_MIX, 0x00 },
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xd0 */ 183 { ADAU1373_LHP_MIX, 0x00 },
183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 184 { ADAU1373_RHP_MIX, 0x00 },
184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, /* 0xe0 */ 185 { ADAU1373_EP_MIX, 0x00 },
185 0x00, 0x1f, 0x0f, 0x00, 0x00, 186 { ADAU1373_HP_CTRL, 0x00 },
187 { ADAU1373_HP_CTRL2, 0x00 },
188 { ADAU1373_LS_CTRL, 0x00 },
189 { ADAU1373_EP_CTRL, 0x00 },
190 { ADAU1373_MICBIAS_CTRL1, 0x00 },
191 { ADAU1373_MICBIAS_CTRL2, 0x00 },
192 { ADAU1373_OUTPUT_CTRL, 0x00 },
193 { ADAU1373_PWDN_CTRL1, 0x00 },
194 { ADAU1373_PWDN_CTRL2, 0x00 },
195 { ADAU1373_PWDN_CTRL3, 0x00 },
196 { ADAU1373_DPLL_CTRL(0), 0x00 },
197 { ADAU1373_PLL_CTRL1(0), 0x00 },
198 { ADAU1373_PLL_CTRL2(0), 0x00 },
199 { ADAU1373_PLL_CTRL3(0), 0x00 },
200 { ADAU1373_PLL_CTRL4(0), 0x00 },
201 { ADAU1373_PLL_CTRL5(0), 0x00 },
202 { ADAU1373_PLL_CTRL6(0), 0x02 },
203 { ADAU1373_DPLL_CTRL(1), 0x00 },
204 { ADAU1373_PLL_CTRL1(1), 0x00 },
205 { ADAU1373_PLL_CTRL2(1), 0x00 },
206 { ADAU1373_PLL_CTRL3(1), 0x00 },
207 { ADAU1373_PLL_CTRL4(1), 0x00 },
208 { ADAU1373_PLL_CTRL5(1), 0x00 },
209 { ADAU1373_PLL_CTRL6(1), 0x02 },
210 { ADAU1373_HEADDECT, 0x00 },
211 { ADAU1373_ADC_CTRL, 0x00 },
212 { ADAU1373_CLK_SRC_DIV(0), 0x00 },
213 { ADAU1373_CLK_SRC_DIV(1), 0x00 },
214 { ADAU1373_DAI(0), 0x0a },
215 { ADAU1373_DAI(1), 0x0a },
216 { ADAU1373_DAI(2), 0x0a },
217 { ADAU1373_BCLKDIV(0), 0x00 },
218 { ADAU1373_BCLKDIV(1), 0x00 },
219 { ADAU1373_BCLKDIV(2), 0x00 },
220 { ADAU1373_SRC_RATIOA(0), 0x00 },
221 { ADAU1373_SRC_RATIOB(0), 0x00 },
222 { ADAU1373_SRC_RATIOA(1), 0x00 },
223 { ADAU1373_SRC_RATIOB(1), 0x00 },
224 { ADAU1373_SRC_RATIOA(2), 0x00 },
225 { ADAU1373_SRC_RATIOB(2), 0x00 },
226 { ADAU1373_DEEMP_CTRL, 0x00 },
227 { ADAU1373_SRC_DAI_CTRL(0), 0x08 },
228 { ADAU1373_SRC_DAI_CTRL(1), 0x08 },
229 { ADAU1373_SRC_DAI_CTRL(2), 0x08 },
230 { ADAU1373_DIN_MIX_CTRL(0), 0x00 },
231 { ADAU1373_DIN_MIX_CTRL(1), 0x00 },
232 { ADAU1373_DIN_MIX_CTRL(2), 0x00 },
233 { ADAU1373_DIN_MIX_CTRL(3), 0x00 },
234 { ADAU1373_DIN_MIX_CTRL(4), 0x00 },
235 { ADAU1373_DOUT_MIX_CTRL(0), 0x00 },
236 { ADAU1373_DOUT_MIX_CTRL(1), 0x00 },
237 { ADAU1373_DOUT_MIX_CTRL(2), 0x00 },
238 { ADAU1373_DOUT_MIX_CTRL(3), 0x00 },
239 { ADAU1373_DOUT_MIX_CTRL(4), 0x00 },
240 { ADAU1373_DAI_PBL_VOL(0), 0x00 },
241 { ADAU1373_DAI_PBR_VOL(0), 0x00 },
242 { ADAU1373_DAI_PBL_VOL(1), 0x00 },
243 { ADAU1373_DAI_PBR_VOL(1), 0x00 },
244 { ADAU1373_DAI_PBL_VOL(2), 0x00 },
245 { ADAU1373_DAI_PBR_VOL(2), 0x00 },
246 { ADAU1373_DAI_RECL_VOL(0), 0x00 },
247 { ADAU1373_DAI_RECR_VOL(0), 0x00 },
248 { ADAU1373_DAI_RECL_VOL(1), 0x00 },
249 { ADAU1373_DAI_RECR_VOL(1), 0x00 },
250 { ADAU1373_DAI_RECL_VOL(2), 0x00 },
251 { ADAU1373_DAI_RECR_VOL(2), 0x00 },
252 { ADAU1373_DAC1_PBL_VOL, 0x00 },
253 { ADAU1373_DAC1_PBR_VOL, 0x00 },
254 { ADAU1373_DAC2_PBL_VOL, 0x00 },
255 { ADAU1373_DAC2_PBR_VOL, 0x00 },
256 { ADAU1373_ADC_RECL_VOL, 0x00 },
257 { ADAU1373_ADC_RECR_VOL, 0x00 },
258 { ADAU1373_DMIC_RECL_VOL, 0x00 },
259 { ADAU1373_DMIC_RECR_VOL, 0x00 },
260 { ADAU1373_VOL_GAIN1, 0x00 },
261 { ADAU1373_VOL_GAIN2, 0x00 },
262 { ADAU1373_VOL_GAIN3, 0x00 },
263 { ADAU1373_HPF_CTRL, 0x00 },
264 { ADAU1373_BASS1, 0x00 },
265 { ADAU1373_BASS2, 0x00 },
266 { ADAU1373_DRC(0) + 0x0, 0x78 },
267 { ADAU1373_DRC(0) + 0x1, 0x18 },
268 { ADAU1373_DRC(0) + 0x2, 0x00 },
269 { ADAU1373_DRC(0) + 0x3, 0x00 },
270 { ADAU1373_DRC(0) + 0x4, 0x00 },
271 { ADAU1373_DRC(0) + 0x5, 0xc0 },
272 { ADAU1373_DRC(0) + 0x6, 0x00 },
273 { ADAU1373_DRC(0) + 0x7, 0x00 },
274 { ADAU1373_DRC(0) + 0x8, 0x00 },
275 { ADAU1373_DRC(0) + 0x9, 0xc0 },
276 { ADAU1373_DRC(0) + 0xa, 0x88 },
277 { ADAU1373_DRC(0) + 0xb, 0x7a },
278 { ADAU1373_DRC(0) + 0xc, 0xdf },
279 { ADAU1373_DRC(0) + 0xd, 0x20 },
280 { ADAU1373_DRC(0) + 0xe, 0x00 },
281 { ADAU1373_DRC(0) + 0xf, 0x00 },
282 { ADAU1373_DRC(1) + 0x0, 0x78 },
283 { ADAU1373_DRC(1) + 0x1, 0x18 },
284 { ADAU1373_DRC(1) + 0x2, 0x00 },
285 { ADAU1373_DRC(1) + 0x3, 0x00 },
286 { ADAU1373_DRC(1) + 0x4, 0x00 },
287 { ADAU1373_DRC(1) + 0x5, 0xc0 },
288 { ADAU1373_DRC(1) + 0x6, 0x00 },
289 { ADAU1373_DRC(1) + 0x7, 0x00 },
290 { ADAU1373_DRC(1) + 0x8, 0x00 },
291 { ADAU1373_DRC(1) + 0x9, 0xc0 },
292 { ADAU1373_DRC(1) + 0xa, 0x88 },
293 { ADAU1373_DRC(1) + 0xb, 0x7a },
294 { ADAU1373_DRC(1) + 0xc, 0xdf },
295 { ADAU1373_DRC(1) + 0xd, 0x20 },
296 { ADAU1373_DRC(1) + 0xe, 0x00 },
297 { ADAU1373_DRC(1) + 0xf, 0x00 },
298 { ADAU1373_DRC(2) + 0x0, 0x78 },
299 { ADAU1373_DRC(2) + 0x1, 0x18 },
300 { ADAU1373_DRC(2) + 0x2, 0x00 },
301 { ADAU1373_DRC(2) + 0x3, 0x00 },
302 { ADAU1373_DRC(2) + 0x4, 0x00 },
303 { ADAU1373_DRC(2) + 0x5, 0xc0 },
304 { ADAU1373_DRC(2) + 0x6, 0x00 },
305 { ADAU1373_DRC(2) + 0x7, 0x00 },
306 { ADAU1373_DRC(2) + 0x8, 0x00 },
307 { ADAU1373_DRC(2) + 0x9, 0xc0 },
308 { ADAU1373_DRC(2) + 0xa, 0x88 },
309 { ADAU1373_DRC(2) + 0xb, 0x7a },
310 { ADAU1373_DRC(2) + 0xc, 0xdf },
311 { ADAU1373_DRC(2) + 0xd, 0x20 },
312 { ADAU1373_DRC(2) + 0xe, 0x00 },
313 { ADAU1373_DRC(2) + 0xf, 0x00 },
314 { ADAU1373_3D_CTRL1, 0x00 },
315 { ADAU1373_3D_CTRL2, 0x00 },
316 { ADAU1373_FDSP_SEL1, 0x00 },
317 { ADAU1373_FDSP_SEL2, 0x00 },
318 { ADAU1373_FDSP_SEL2, 0x00 },
319 { ADAU1373_FDSP_SEL4, 0x00 },
320 { ADAU1373_DIGMICCTRL, 0x00 },
321 { ADAU1373_DIGEN, 0x00 },
186}; 322};
187 323
188static const unsigned int adau1373_out_tlv[] = { 324static const unsigned int adau1373_out_tlv[] = {
@@ -418,6 +554,7 @@ static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
418 struct snd_kcontrol *kcontrol, int event) 554 struct snd_kcontrol *kcontrol, int event)
419{ 555{
420 struct snd_soc_codec *codec = w->codec; 556 struct snd_soc_codec *codec = w->codec;
557 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
421 unsigned int pll_id = w->name[3] - '1'; 558 unsigned int pll_id = w->name[3] - '1';
422 unsigned int val; 559 unsigned int val;
423 560
@@ -426,7 +563,7 @@ static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
426 else 563 else
427 val = 0; 564 val = 0;
428 565
429 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 566 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
430 ADAU1373_PLL_CTRL6_PLL_EN, val); 567 ADAU1373_PLL_CTRL6_PLL_EN, val);
431 568
432 if (SND_SOC_DAPM_EVENT_ON(event)) 569 if (SND_SOC_DAPM_EVENT_ON(event))
@@ -938,7 +1075,7 @@ static int adau1373_hw_params(struct snd_pcm_substream *substream,
938 1075
939 adau1373_dai->enable_src = (div != 0); 1076 adau1373_dai->enable_src = (div != 0);
940 1077
941 snd_soc_update_bits(codec, ADAU1373_BCLKDIV(dai->id), 1078 regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
942 ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK, 1079 ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK,
943 (div << 2) | ADAU1373_BCLKDIV_64); 1080 (div << 2) | ADAU1373_BCLKDIV_64);
944 1081
@@ -959,7 +1096,7 @@ static int adau1373_hw_params(struct snd_pcm_substream *substream,
959 return -EINVAL; 1096 return -EINVAL;
960 } 1097 }
961 1098
962 return snd_soc_update_bits(codec, ADAU1373_DAI(dai->id), 1099 return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
963 ADAU1373_DAI_WLEN_MASK, ctrl); 1100 ADAU1373_DAI_WLEN_MASK, ctrl);
964} 1101}
965 1102
@@ -1016,7 +1153,7 @@ static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1016 return -EINVAL; 1153 return -EINVAL;
1017 } 1154 }
1018 1155
1019 snd_soc_update_bits(codec, ADAU1373_DAI(dai->id), 1156 regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1020 ~ADAU1373_DAI_WLEN_MASK, ctrl); 1157 ~ADAU1373_DAI_WLEN_MASK, ctrl);
1021 1158
1022 return 0; 1159 return 0;
@@ -1039,7 +1176,7 @@ static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,
1039 adau1373_dai->sysclk = freq; 1176 adau1373_dai->sysclk = freq;
1040 adau1373_dai->clk_src = clk_id; 1177 adau1373_dai->clk_src = clk_id;
1041 1178
1042 snd_soc_update_bits(dai->codec, ADAU1373_BCLKDIV(dai->id), 1179 regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1043 ADAU1373_BCLKDIV_SOURCE, clk_id << 5); 1180 ADAU1373_BCLKDIV_SOURCE, clk_id << 5);
1044 1181
1045 return 0; 1182 return 0;
@@ -1120,6 +1257,7 @@ static struct snd_soc_dai_driver adau1373_dai_driver[] = {
1120static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id, 1257static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id,
1121 int source, unsigned int freq_in, unsigned int freq_out) 1258 int source, unsigned int freq_in, unsigned int freq_out)
1122{ 1259{
1260 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1123 unsigned int dpll_div = 0; 1261 unsigned int dpll_div = 0;
1124 unsigned int x, r, n, m, i, j, mode; 1262 unsigned int x, r, n, m, i, j, mode;
1125 1263
@@ -1187,36 +1325,36 @@ static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id,
1187 1325
1188 if (dpll_div) { 1326 if (dpll_div) {
1189 dpll_div = 11 - dpll_div; 1327 dpll_div = 11 - dpll_div;
1190 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 1328 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1191 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0); 1329 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0);
1192 } else { 1330 } else {
1193 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 1331 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1194 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 1332 ADAU1373_PLL_CTRL6_DPLL_BYPASS,
1195 ADAU1373_PLL_CTRL6_DPLL_BYPASS); 1333 ADAU1373_PLL_CTRL6_DPLL_BYPASS);
1196 } 1334 }
1197 1335
1198 snd_soc_write(codec, ADAU1373_DPLL_CTRL(pll_id), 1336 regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
1199 (source << 4) | dpll_div); 1337 (source << 4) | dpll_div);
1200 snd_soc_write(codec, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff); 1338 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff);
1201 snd_soc_write(codec, ADAU1373_PLL_CTRL2(pll_id), m & 0xff); 1339 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), m & 0xff);
1202 snd_soc_write(codec, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff); 1340 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff);
1203 snd_soc_write(codec, ADAU1373_PLL_CTRL4(pll_id), n & 0xff); 1341 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), n & 0xff);
1204 snd_soc_write(codec, ADAU1373_PLL_CTRL5(pll_id), 1342 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id),
1205 (r << 3) | (x << 1) | mode); 1343 (r << 3) | (x << 1) | mode);
1206 1344
1207 /* Set sysclk to pll_rate / 4 */ 1345 /* Set sysclk to pll_rate / 4 */
1208 snd_soc_update_bits(codec, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09); 1346 regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
1209 1347
1210 return 0; 1348 return 0;
1211} 1349}
1212 1350
1213static void adau1373_load_drc_settings(struct snd_soc_codec *codec, 1351static void adau1373_load_drc_settings(struct adau1373 *adau1373,
1214 unsigned int nr, uint8_t *drc) 1352 unsigned int nr, uint8_t *drc)
1215{ 1353{
1216 unsigned int i; 1354 unsigned int i;
1217 1355
1218 for (i = 0; i < ADAU1373_DRC_SIZE; ++i) 1356 for (i = 0; i < ADAU1373_DRC_SIZE; ++i)
1219 snd_soc_write(codec, ADAU1373_DRC(nr) + i, drc[i]); 1357 regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]);
1220} 1358}
1221 1359
1222static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias) 1360static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
@@ -1235,13 +1373,14 @@ static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
1235 1373
1236static int adau1373_probe(struct snd_soc_codec *codec) 1374static int adau1373_probe(struct snd_soc_codec *codec)
1237{ 1375{
1376 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1238 struct adau1373_platform_data *pdata = codec->dev->platform_data; 1377 struct adau1373_platform_data *pdata = codec->dev->platform_data;
1239 bool lineout_differential = false; 1378 bool lineout_differential = false;
1240 unsigned int val; 1379 unsigned int val;
1241 int ret; 1380 int ret;
1242 int i; 1381 int i;
1243 1382
1244 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 1383 ret = snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP);
1245 if (ret) { 1384 if (ret) {
1246 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret); 1385 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret);
1247 return ret; 1386 return ret;
@@ -1256,7 +1395,7 @@ static int adau1373_probe(struct snd_soc_codec *codec)
1256 return -EINVAL; 1395 return -EINVAL;
1257 1396
1258 for (i = 0; i < pdata->num_drc; ++i) { 1397 for (i = 0; i < pdata->num_drc; ++i) {
1259 adau1373_load_drc_settings(codec, i, 1398 adau1373_load_drc_settings(adau1373, i,
1260 pdata->drc_setting[i]); 1399 pdata->drc_setting[i]);
1261 } 1400 }
1262 1401
@@ -1268,18 +1407,18 @@ static int adau1373_probe(struct snd_soc_codec *codec)
1268 if (pdata->input_differential[i]) 1407 if (pdata->input_differential[i])
1269 val |= BIT(i); 1408 val |= BIT(i);
1270 } 1409 }
1271 snd_soc_write(codec, ADAU1373_INPUT_MODE, val); 1410 regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val);
1272 1411
1273 val = 0; 1412 val = 0;
1274 if (pdata->lineout_differential) 1413 if (pdata->lineout_differential)
1275 val |= ADAU1373_OUTPUT_CTRL_LDIFF; 1414 val |= ADAU1373_OUTPUT_CTRL_LDIFF;
1276 if (pdata->lineout_ground_sense) 1415 if (pdata->lineout_ground_sense)
1277 val |= ADAU1373_OUTPUT_CTRL_LNFBEN; 1416 val |= ADAU1373_OUTPUT_CTRL_LNFBEN;
1278 snd_soc_write(codec, ADAU1373_OUTPUT_CTRL, val); 1417 regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val);
1279 1418
1280 lineout_differential = pdata->lineout_differential; 1419 lineout_differential = pdata->lineout_differential;
1281 1420
1282 snd_soc_write(codec, ADAU1373_EP_CTRL, 1421 regmap_write(adau1373->regmap, ADAU1373_EP_CTRL,
1283 (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) | 1422 (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) |
1284 (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET)); 1423 (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET));
1285 } 1424 }
@@ -1289,7 +1428,7 @@ static int adau1373_probe(struct snd_soc_codec *codec)
1289 ARRAY_SIZE(adau1373_lineout2_controls)); 1428 ARRAY_SIZE(adau1373_lineout2_controls));
1290 } 1429 }
1291 1430
1292 snd_soc_write(codec, ADAU1373_ADC_CTRL, 1431 regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL,
1293 ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT); 1432 ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT);
1294 1433
1295 return 0; 1434 return 0;
@@ -1298,17 +1437,19 @@ static int adau1373_probe(struct snd_soc_codec *codec)
1298static int adau1373_set_bias_level(struct snd_soc_codec *codec, 1437static int adau1373_set_bias_level(struct snd_soc_codec *codec,
1299 enum snd_soc_bias_level level) 1438 enum snd_soc_bias_level level)
1300{ 1439{
1440 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1441
1301 switch (level) { 1442 switch (level) {
1302 case SND_SOC_BIAS_ON: 1443 case SND_SOC_BIAS_ON:
1303 break; 1444 break;
1304 case SND_SOC_BIAS_PREPARE: 1445 case SND_SOC_BIAS_PREPARE:
1305 break; 1446 break;
1306 case SND_SOC_BIAS_STANDBY: 1447 case SND_SOC_BIAS_STANDBY:
1307 snd_soc_update_bits(codec, ADAU1373_PWDN_CTRL3, 1448 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1308 ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN); 1449 ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN);
1309 break; 1450 break;
1310 case SND_SOC_BIAS_OFF: 1451 case SND_SOC_BIAS_OFF:
1311 snd_soc_update_bits(codec, ADAU1373_PWDN_CTRL3, 1452 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1312 ADAU1373_PWDN_CTRL3_PWR_EN, 0); 1453 ADAU1373_PWDN_CTRL3_PWR_EN, 0);
1313 break; 1454 break;
1314 } 1455 }
@@ -1324,17 +1465,49 @@ static int adau1373_remove(struct snd_soc_codec *codec)
1324 1465
1325static int adau1373_suspend(struct snd_soc_codec *codec) 1466static int adau1373_suspend(struct snd_soc_codec *codec)
1326{ 1467{
1327 return adau1373_set_bias_level(codec, SND_SOC_BIAS_OFF); 1468 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1469 int ret;
1470
1471 ret = adau1373_set_bias_level(codec, SND_SOC_BIAS_OFF);
1472 regcache_cache_only(adau1373->regmap, true);
1473
1474 return ret;
1328} 1475}
1329 1476
1330static int adau1373_resume(struct snd_soc_codec *codec) 1477static int adau1373_resume(struct snd_soc_codec *codec)
1331{ 1478{
1479 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1480
1481 regcache_cache_only(adau1373->regmap, false);
1332 adau1373_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1482 adau1373_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1333 snd_soc_cache_sync(codec); 1483 regcache_sync(adau1373->regmap);
1334 1484
1335 return 0; 1485 return 0;
1336} 1486}
1337 1487
1488static bool adau1373_register_volatile(struct device *dev, unsigned int reg)
1489{
1490 switch (reg) {
1491 case ADAU1373_SOFT_RESET:
1492 case ADAU1373_ADC_DAC_STATUS:
1493 return true;
1494 default:
1495 return false;
1496 }
1497}
1498
1499static const struct regmap_config adau1373_regmap_config = {
1500 .val_bits = 8,
1501 .reg_bits = 8,
1502
1503 .volatile_reg = adau1373_register_volatile,
1504 .max_register = ADAU1373_SOFT_RESET,
1505
1506 .cache_type = REGCACHE_RBTREE,
1507 .reg_defaults = adau1373_reg_defaults,
1508 .num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults),
1509};
1510
1338static struct snd_soc_codec_driver adau1373_codec_driver = { 1511static struct snd_soc_codec_driver adau1373_codec_driver = {
1339 .probe = adau1373_probe, 1512 .probe = adau1373_probe,
1340 .remove = adau1373_remove, 1513 .remove = adau1373_remove,
@@ -1342,9 +1515,6 @@ static struct snd_soc_codec_driver adau1373_codec_driver = {
1342 .resume = adau1373_resume, 1515 .resume = adau1373_resume,
1343 .set_bias_level = adau1373_set_bias_level, 1516 .set_bias_level = adau1373_set_bias_level,
1344 .idle_bias_off = true, 1517 .idle_bias_off = true,
1345 .reg_cache_size = ARRAY_SIZE(adau1373_default_regs),
1346 .reg_cache_default = adau1373_default_regs,
1347 .reg_word_size = sizeof(uint8_t),
1348 1518
1349 .set_pll = adau1373_set_pll, 1519 .set_pll = adau1373_set_pll,
1350 1520
@@ -1366,6 +1536,11 @@ static int adau1373_i2c_probe(struct i2c_client *client,
1366 if (!adau1373) 1536 if (!adau1373)
1367 return -ENOMEM; 1537 return -ENOMEM;
1368 1538
1539 adau1373->regmap = devm_regmap_init_i2c(client,
1540 &adau1373_regmap_config);
1541 if (IS_ERR(adau1373->regmap))
1542 return PTR_ERR(adau1373->regmap);
1543
1369 dev_set_drvdata(&client->dev, adau1373); 1544 dev_set_drvdata(&client->dev, adau1373);
1370 1545
1371 ret = snd_soc_register_codec(&client->dev, &adau1373_codec_driver, 1546 ret = snd_soc_register_codec(&client->dev, &adau1373_codec_driver,
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 23:07:56 -0500