[SCSI] qla4xxx: Clean-up and optimize macros

Remove following unused define:-

QLA82XX_MINIDUMP_OCM0_SIZE
QLA82XX_MINIDUMP_L1C_SIZE
QLA82XX_MINIDUMP_L2C_SIZE
QLA82XX_MINIDUMP_COMMON_STR_SIZE
QLA82XX_MINIDUMP_FCOE_STR_SIZE
QLA82XX_MINIDUMP_MEM_SIZE
QLA82XX_MAX_ENTRY_HDR

Added following new define to optimize code:-

MIU_TA_CTL_WRITE_ENABLE
MIU_TA_CTL_WRITE_START
MIU_TA_CTL_START_ENABLE

Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
Reviewed-by: Mike Christie <michaelc@cs.wisc.edu>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>

2 files changed, 14 insertions, 27 deletions

diff --git a/drivers/scsi/qla4xxx/ql4_nx.c b/drivers/scsi/qla4xxx/ql4_nx.c
index e4801845b769..84b039f9e9b5 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.c
+++ b/drivers/scsi/qla4xxx/ql4_nx.c
@@ -562,10 +562,6 @@ qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
         return 1;
 }
 
-/*  PCI Windowing for DDR regions.  */
-#define QLA8XXX_ADDR_IN_RANGE(addr, low, high)            \
-        (((addr) <= (high)) && ((addr) >= (low)))
-
 /*
 * check memory access boundary.
 * used by test agent. support ddr access only for now
@@ -1276,7 +1272,7 @@ qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
                 temp = MIU_TA_CTL_ENABLE;
                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
-                temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
+                temp = MIU_TA_CTL_START_ENABLE;
                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
 
                 for (j = 0; j < MAX_CTL_CHECK; j++) {
@@ -1410,9 +1406,9 @@ qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
                     temp);
 
-                temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
+                temp = MIU_TA_CTL_WRITE_ENABLE;
                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
-                temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
+                temp = MIU_TA_CTL_WRITE_START;
                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
 
                 for (j = 0; j < MAX_CTL_CHECK; j++) {
@@ -2041,7 +2037,7 @@ static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
                 r_value = MIU_TA_CTL_ENABLE;
                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
-                r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
+                r_value = MIU_TA_CTL_START_ENABLE;
                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
 
                 for (j = 0; j < MAX_CTL_CHECK; j++) {
diff --git a/drivers/scsi/qla4xxx/ql4_nx.h b/drivers/scsi/qla4xxx/ql4_nx.h
index 1936c8168332..16c5ae6d271a 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.h
+++ b/drivers/scsi/qla4xxx/ql4_nx.h
@@ -517,6 +517,10 @@ enum {
 #define QLA82XX_PCI_QDR_NET             (unsigned long)0x04000000
 #define QLA82XX_PCI_QDR_NET_MAX         (unsigned long)0x043fffff
 
+/*  PCI Windowing for DDR regions.  */
+#define QLA8XXX_ADDR_IN_RANGE(addr, low, high)            \
+        (((addr) <= (high)) && ((addr) >= (low)))
+
 /*
  *   Register offsets for MN
  */
@@ -540,6 +544,11 @@ enum {
 #define MIU_TA_CTL_WRITE        4
 #define MIU_TA_CTL_BUSY         8
 
+#define MIU_TA_CTL_WRITE_ENABLE         (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
+#define MIU_TA_CTL_WRITE_START          (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE |\
+                                         MIU_TA_CTL_START)
+#define MIU_TA_CTL_START_ENABLE         (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
+
 /*CAM RAM */
 # define QLA82XX_CAM_RAM_BASE   (QLA82XX_CRB_CAM + 0x02000)
 # define QLA82XX_CAM_RAM(reg)   (QLA82XX_CAM_RAM_BASE + (reg))
@@ -565,11 +574,10 @@ enum {
 /* Driver Coexistence Defines */
 #define QLA82XX_CRB_DRV_ACTIVE          (QLA82XX_CAM_RAM(0x138))
 #define QLA82XX_CRB_DEV_STATE           (QLA82XX_CAM_RAM(0x140))
-#define QLA82XX_CRB_DEV_PART_INFO       (QLA82XX_CAM_RAM(0x14c))
-#define QLA82XX_CRB_DRV_IDC_VERSION     (QLA82XX_CAM_RAM(0x174))
 #define QLA82XX_CRB_DRV_STATE           (QLA82XX_CAM_RAM(0x144))
 #define QLA82XX_CRB_DRV_SCRATCH         (QLA82XX_CAM_RAM(0x148))
 #define QLA82XX_CRB_DEV_PART_INFO       (QLA82XX_CAM_RAM(0x14c))
+#define QLA82XX_CRB_DRV_IDC_VERSION     (QLA82XX_CAM_RAM(0x174))
 
 /* Every driver should use these Device State */
 #define QLA8XXX_DEV_COLD                1
@@ -956,23 +964,6 @@ struct qla8xxx_minidump_entry_queue {
         } rd_strd;
 };
 
-#define QLA82XX_MINIDUMP_OCM0_SIZE              (256 * 1024)
-#define QLA82XX_MINIDUMP_L1C_SIZE               (256 * 1024)
-#define QLA82XX_MINIDUMP_L2C_SIZE               1572864
-#define QLA82XX_MINIDUMP_COMMON_STR_SIZE        0
-#define QLA82XX_MINIDUMP_FCOE_STR_SIZE          0
-#define QLA82XX_MINIDUMP_MEM_SIZE               0
-#define QLA82XX_MAX_ENTRY_HDR                   4
-
-struct qla82xx_minidump {
-        uint32_t md_ocm0_data[QLA82XX_MINIDUMP_OCM0_SIZE];
-        uint32_t md_l1c_data[QLA82XX_MINIDUMP_L1C_SIZE];
-        uint32_t md_l2c_data[QLA82XX_MINIDUMP_L2C_SIZE];
-        uint32_t md_cs_data[QLA82XX_MINIDUMP_COMMON_STR_SIZE];
-        uint32_t md_fcoes_data[QLA82XX_MINIDUMP_FCOE_STR_SIZE];
-        uint32_t md_mem_data[QLA82XX_MINIDUMP_MEM_SIZE];
-};
-
 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE        0x129
 #define RQST_TMPLT_SIZE                         0x0
 #define RQST_TMPLT                              0x1