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authorBen Skeggs <bskeggs@redhat.com>2014-09-14 22:30:08 -0400
committerBen Skeggs <bskeggs@redhat.com>2014-09-15 08:25:15 -0400
commitc378eb746167e0e96e9a2da72781c0d409a8d94e (patch)
tree8b49d35636582cb9651957f23eac43b553e0c834
parenta407318913b11362e10d0948ae82de6edaf98a9e (diff)
drm/nouveau/bios: parse older ramcfg/timing data like we do newer ones
Done after discussion with Roy. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h162
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/fb.h5
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c19
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/timing.c6
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c87
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c16
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c21
7 files changed, 184 insertions, 132 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
index 7e5b06733143..a685bbd04568 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
@@ -8,76 +8,114 @@ struct nvbios_ramcfg {
8 unsigned rammap_hdr; 8 unsigned rammap_hdr;
9 unsigned rammap_min; 9 unsigned rammap_min;
10 unsigned rammap_max; 10 unsigned rammap_max;
11 unsigned rammap_11_08_01:1; 11 union {
12 unsigned rammap_11_08_0c:2; 12 struct {
13 unsigned rammap_11_08_10:1; 13 unsigned rammap_10_04_02:1;
14 unsigned rammap_11_09_01ff:9; 14 unsigned rammap_10_04_08:1;
15 unsigned rammap_11_0a_03fe:9; 15 };
16 unsigned rammap_11_0a_0400:1; 16 struct {
17 unsigned rammap_11_0a_0800:1; 17 unsigned rammap_11_08_01:1;
18 unsigned rammap_11_0b_01f0:5; 18 unsigned rammap_11_08_0c:2;
19 unsigned rammap_11_0b_0200:1; 19 unsigned rammap_11_08_10:1;
20 unsigned rammap_11_0b_0400:1; 20 unsigned rammap_11_09_01ff:9;
21 unsigned rammap_11_0b_0800:1; 21 unsigned rammap_11_0a_03fe:9;
22 unsigned rammap_11_0d:8; 22 unsigned rammap_11_0a_0400:1;
23 unsigned rammap_11_0e:8; 23 unsigned rammap_11_0a_0800:1;
24 unsigned rammap_11_0f:8; 24 unsigned rammap_11_0b_01f0:5;
25 unsigned rammap_11_11_0c:2; 25 unsigned rammap_11_0b_0200:1;
26 unsigned rammap_11_0b_0400:1;
27 unsigned rammap_11_0b_0800:1;
28 unsigned rammap_11_0d:8;
29 unsigned rammap_11_0e:8;
30 unsigned rammap_11_0f:8;
31 unsigned rammap_11_11_0c:2;
32 };
33 };
26 34
27 unsigned ramcfg_ver; 35 unsigned ramcfg_ver;
28 unsigned ramcfg_hdr; 36 unsigned ramcfg_hdr;
29 unsigned ramcfg_timing; 37 unsigned ramcfg_timing;
30 unsigned ramcfg_11_01_01:1; 38 union {
31 unsigned ramcfg_11_01_02:1; 39 struct {
32 unsigned ramcfg_11_01_04:1; 40 unsigned ramcfg_10_02_01:1;
33 unsigned ramcfg_11_01_08:1; 41 unsigned ramcfg_10_02_02:1;
34 unsigned ramcfg_11_01_10:1; 42 unsigned ramcfg_10_02_04:1;
35 unsigned ramcfg_11_01_20:1; 43 unsigned ramcfg_10_02_08:1;
36 unsigned ramcfg_11_01_40:1; 44 unsigned ramcfg_10_02_10:1;
37 unsigned ramcfg_11_01_80:1; 45 unsigned ramcfg_10_02_20:1;
38 unsigned ramcfg_11_02_03:2; 46 unsigned ramcfg_10_02_40:1;
39 unsigned ramcfg_11_02_04:1; 47 unsigned ramcfg_10_03_0f:4;
40 unsigned ramcfg_11_02_08:1; 48 unsigned ramcfg_10_05:8;
41 unsigned ramcfg_11_02_10:1; 49 unsigned ramcfg_10_06:8;
42 unsigned ramcfg_11_02_40:1; 50 unsigned ramcfg_10_07:8;
43 unsigned ramcfg_11_02_80:1; 51 unsigned ramcfg_10_08:8;
44 unsigned ramcfg_11_03_0f:4; 52 unsigned ramcfg_10_09_0f:4;
45 unsigned ramcfg_11_03_30:2; 53 unsigned ramcfg_10_09_f0:4;
46 unsigned ramcfg_11_03_c0:2; 54 };
47 unsigned ramcfg_11_03_f0:4; 55 struct {
48 unsigned ramcfg_11_04:8; 56 unsigned ramcfg_11_01_01:1;
49 unsigned ramcfg_11_06:8; 57 unsigned ramcfg_11_01_02:1;
50 unsigned ramcfg_11_07_02:1; 58 unsigned ramcfg_11_01_04:1;
51 unsigned ramcfg_11_07_04:1; 59 unsigned ramcfg_11_01_08:1;
52 unsigned ramcfg_11_07_08:1; 60 unsigned ramcfg_11_01_10:1;
53 unsigned ramcfg_11_07_10:1; 61 unsigned ramcfg_11_01_20:1;
54 unsigned ramcfg_11_07_40:1; 62 unsigned ramcfg_11_01_40:1;
55 unsigned ramcfg_11_07_80:1; 63 unsigned ramcfg_11_01_80:1;
56 unsigned ramcfg_11_08_01:1; 64 unsigned ramcfg_11_02_03:2;
57 unsigned ramcfg_11_08_02:1; 65 unsigned ramcfg_11_02_04:1;
58 unsigned ramcfg_11_08_04:1; 66 unsigned ramcfg_11_02_08:1;
59 unsigned ramcfg_11_08_08:1; 67 unsigned ramcfg_11_02_10:1;
60 unsigned ramcfg_11_08_10:1; 68 unsigned ramcfg_11_02_40:1;
61 unsigned ramcfg_11_08_20:1; 69 unsigned ramcfg_11_02_80:1;
62 unsigned ramcfg_11_09:8; 70 unsigned ramcfg_11_03_0f:4;
71 unsigned ramcfg_11_03_30:2;
72 unsigned ramcfg_11_03_c0:2;
73 unsigned ramcfg_11_03_f0:4;
74 unsigned ramcfg_11_04:8;
75 unsigned ramcfg_11_06:8;
76 unsigned ramcfg_11_07_02:1;
77 unsigned ramcfg_11_07_04:1;
78 unsigned ramcfg_11_07_08:1;
79 unsigned ramcfg_11_07_10:1;
80 unsigned ramcfg_11_07_40:1;
81 unsigned ramcfg_11_07_80:1;
82 unsigned ramcfg_11_08_01:1;
83 unsigned ramcfg_11_08_02:1;
84 unsigned ramcfg_11_08_04:1;
85 unsigned ramcfg_11_08_08:1;
86 unsigned ramcfg_11_08_10:1;
87 unsigned ramcfg_11_08_20:1;
88 unsigned ramcfg_11_09:8;
89 };
90 };
63 91
64 unsigned timing_ver; 92 unsigned timing_ver;
65 unsigned timing_hdr; 93 unsigned timing_hdr;
66 unsigned timing[11]; 94 unsigned timing[11];
67 unsigned timing_20_2e_03:2; 95 union {
68 unsigned timing_20_2e_30:2; 96 struct {
69 unsigned timing_20_2e_c0:2; 97 unsigned timing_10_WR:8;
70 unsigned timing_20_2f_03:2; 98 unsigned timing_10_CL:8;
71 unsigned timing_20_2c_003f:6; 99 unsigned timing_10_ODT:3;
72 unsigned timing_20_2c_1fc0:7; 100 unsigned timing_10_CWL:8;
73 unsigned timing_20_30_f8:5; 101 };
74 unsigned timing_20_30_07:3; 102 struct {
75 unsigned timing_20_31_0007:3; 103 unsigned timing_20_2e_03:2;
76 unsigned timing_20_31_0078:4; 104 unsigned timing_20_2e_30:2;
77 unsigned timing_20_31_0780:4; 105 unsigned timing_20_2e_c0:2;
78 unsigned timing_20_31_0800:1; 106 unsigned timing_20_2f_03:2;
79 unsigned timing_20_31_7000:3; 107 unsigned timing_20_2c_003f:6;
80 unsigned timing_20_31_8000:1; 108 unsigned timing_20_2c_1fc0:7;
109 unsigned timing_20_30_f8:5;
110 unsigned timing_20_30_07:3;
111 unsigned timing_20_31_0007:3;
112 unsigned timing_20_31_0078:4;
113 unsigned timing_20_31_0780:4;
114 unsigned timing_20_31_0800:1;
115 unsigned timing_20_31_7000:3;
116 unsigned timing_20_31_8000:1;
117 };
118 };
81}; 119};
82 120
83u8 nvbios_ramcfg_count(struct nouveau_bios *); 121u8 nvbios_ramcfg_count(struct nouveau_bios *);
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
index 507c3b44e560..8d0032f15205 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
@@ -146,11 +146,6 @@ struct nouveau_ram {
146 int (*calc)(struct nouveau_fb *, u32 freq); 146 int (*calc)(struct nouveau_fb *, u32 freq);
147 int (*prog)(struct nouveau_fb *); 147 int (*prog)(struct nouveau_fb *);
148 void (*tidy)(struct nouveau_fb *); 148 void (*tidy)(struct nouveau_fb *);
149 struct {
150 u8 version;
151 u32 data;
152 u8 size;
153 } rammap, ramcfg, timing;
154 u32 freq; 149 u32 freq;
155 u32 mr[16]; 150 u32 mr[16];
156 u32 mr1_nuts; 151 u32 mr1_nuts;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
index ae3d956aec99..585e69331ccc 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
@@ -87,6 +87,8 @@ nvbios_rammapEp(struct nouveau_bios *bios, int idx,
87 case 0x10: 87 case 0x10:
88 p->rammap_min = nv_ro16(bios, data + 0x00); 88 p->rammap_min = nv_ro16(bios, data + 0x00);
89 p->rammap_max = nv_ro16(bios, data + 0x02); 89 p->rammap_max = nv_ro16(bios, data + 0x02);
90 p->rammap_10_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1;
91 p->rammap_10_04_08 = (nv_ro08(bios, data + 0x04) & 0x08) >> 3;
90 break; 92 break;
91 case 0x11: 93 case 0x11:
92 p->rammap_min = nv_ro16(bios, data + 0x00); 94 p->rammap_min = nv_ro16(bios, data + 0x00);
@@ -152,6 +154,23 @@ nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
152 p->ramcfg_ver = *ver; 154 p->ramcfg_ver = *ver;
153 p->ramcfg_hdr = *hdr; 155 p->ramcfg_hdr = *hdr;
154 switch (!!data * *ver) { 156 switch (!!data * *ver) {
157 case 0x10:
158 p->ramcfg_timing = nv_ro08(bios, data + 0x01);
159 p->ramcfg_10_02_01 = (nv_ro08(bios, data + 0x02) & 0x01) >> 0;
160 p->ramcfg_10_02_02 = (nv_ro08(bios, data + 0x02) & 0x02) >> 1;
161 p->ramcfg_10_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
162 p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
163 p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
164 p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5;
165 p->ramcfg_10_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
166 p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
167 p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0;
168 p->ramcfg_10_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
169 p->ramcfg_10_07 = (nv_ro08(bios, data + 0x07) & 0xff) >> 0;
170 p->ramcfg_10_08 = (nv_ro08(bios, data + 0x08) & 0xff) >> 0;
171 p->ramcfg_10_09_0f = (nv_ro08(bios, data + 0x09) & 0x0f) >> 0;
172 p->ramcfg_10_09_f0 = (nv_ro08(bios, data + 0x09) & 0xf0) >> 4;
173 break;
155 case 0x11: 174 case 0x11:
156 p->ramcfg_timing = nv_ro08(bios, data + 0x00); 175 p->ramcfg_timing = nv_ro08(bios, data + 0x00);
157 p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; 176 p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
index c320bfdd1102..46d955eb51eb 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c
@@ -92,6 +92,12 @@ nvbios_timingEp(struct nouveau_bios *bios, int idx,
92 p->timing_ver = *ver; 92 p->timing_ver = *ver;
93 p->timing_hdr = *hdr; 93 p->timing_hdr = *hdr;
94 switch (!!data * *ver) { 94 switch (!!data * *ver) {
95 case 0x10:
96 p->timing_10_WR = nv_ro08(bios, data + 0x00);
97 p->timing_10_CL = nv_ro08(bios, data + 0x02);
98 p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
99 p->timing_10_CWL = nv_ro08(bios, data + 0x13);
100 break;
95 case 0x20: 101 case 0x20:
96 p->timing[0] = nv_ro32(bios, data + 0x00); 102 p->timing[0] = nv_ro32(bios, data + 0x00);
97 p->timing[1] = nv_ro32(bios, data + 0x04); 103 p->timing[1] = nv_ro32(bios, data + 0x04);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
index c2037b943d00..3601deca0bd5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
@@ -79,21 +79,27 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
79 struct nva3_ram *ram = (void *)pfb->ram; 79 struct nva3_ram *ram = (void *)pfb->ram;
80 struct nva3_ramfuc *fuc = &ram->fuc; 80 struct nva3_ramfuc *fuc = &ram->fuc;
81 struct nva3_clock_info mclk; 81 struct nva3_clock_info mclk;
82 struct nvbios_ramcfg cfg; 82 struct nouveau_ram_data *next;
83 u8 ver, cnt, len, strap; 83 u8 ver, hdr, cnt, len, strap;
84 u32 data; 84 u32 data;
85 struct {
86 u32 data;
87 u8 size;
88 } rammap, ramcfg, timing;
89 u32 r004018, r100760, ctrl; 85 u32 r004018, r100760, ctrl;
90 u32 unk714, unk718, unk71c; 86 u32 unk714, unk718, unk71c;
91 int ret; 87 int ret, i;
88
89 next = &ram->base.target;
90 next->freq = freq;
91 ram->base.next = next;
92 92
93 /* lookup memory config data relevant to the target frequency */ 93 /* lookup memory config data relevant to the target frequency */
94 rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, 94 i = 0;
95 &cnt, &ramcfg.size, &cfg); 95 while ((data = nvbios_rammapEp(bios, i++, &ver, &hdr, &cnt, &len,
96 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { 96 &next->bios))) {
97 if (freq / 1000 >= next->bios.rammap_min &&
98 freq / 1000 <= next->bios.rammap_max)
99 break;
100 }
101
102 if (!data || ver != 0x10 || hdr < 0x0e) {
97 nv_error(pfb, "invalid/missing rammap entry\n"); 103 nv_error(pfb, "invalid/missing rammap entry\n");
98 return -EINVAL; 104 return -EINVAL;
99 } 105 }
@@ -105,23 +111,22 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
105 return -EINVAL; 111 return -EINVAL;
106 } 112 }
107 113
108 ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size); 114 data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
109 if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) { 115 &ver, &hdr, &next->bios);
116 if (!data || ver != 0x10 || hdr < 0x0e) {
110 nv_error(pfb, "invalid/missing ramcfg entry\n"); 117 nv_error(pfb, "invalid/missing ramcfg entry\n");
111 return -EINVAL; 118 return -EINVAL;
112 } 119 }
113 120
114 /* lookup memory timings, if bios says they're present */ 121 /* lookup memory timings, if bios says they're present */
115 strap = nv_ro08(bios, ramcfg.data + 0x01); 122 if (next->bios.ramcfg_timing != 0xff) {
116 if (strap != 0xff) { 123 data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
117 timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, 124 &ver, &hdr, &cnt, &len,
118 &cnt, &len); 125 &next->bios);
119 if (!timing.data || ver != 0x10 || timing.size < 0x19) { 126 if (!data || ver != 0x10 || hdr < 0x19) {
120 nv_error(pfb, "invalid/missing timing entry\n"); 127 nv_error(pfb, "invalid/missing timing entry\n");
121 return -EINVAL; 128 return -EINVAL;
122 } 129 }
123 } else {
124 timing.data = 0;
125 } 130 }
126 131
127 ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); 132 ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
@@ -164,17 +169,17 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
164 ram_mask(fuc, 0x004168, 0x003f3141, ctrl); 169 ram_mask(fuc, 0x004168, 0x003f3141, ctrl);
165 } 170 }
166 171
167 if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) { 172 if (next->bios.ramcfg_10_02_10) {
168 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000); 173 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
169 } else { 174 } else {
170 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000); 175 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
171 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000); 176 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
172 } 177 }
173 178
174 if (!(nv_ro08(bios, rammap.data + 0x04) & 0x02)) 179 if (!next->bios.rammap_10_04_02)
175 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000); 180 ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
176 ram_wr32(fuc, 0x611200, 0x00003300); 181 ram_wr32(fuc, 0x611200, 0x00003300);
177 if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) 182 if (!next->bios.ramcfg_10_02_10)
178 ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/ 183 ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/
179 184
180 ram_wr32(fuc, 0x1002d4, 0x00000001); 185 ram_wr32(fuc, 0x1002d4, 0x00000001);
@@ -203,17 +208,16 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
203 ram_wr32(fuc, 0x004018, 0x0000d000 | r004018); 208 ram_wr32(fuc, 0x004018, 0x0000d000 | r004018);
204 } 209 }
205 210
206 if ( (nv_ro08(bios, rammap.data + 0x04) & 0x08)) { 211 if (next->bios.rammap_10_04_08) {
207 u32 unk5a0 = (nv_ro16(bios, ramcfg.data + 0x05) << 8) | 212 ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
208 nv_ro08(bios, ramcfg.data + 0x05); 213 next->bios.ramcfg_10_05 << 8 |
209 u32 unk5a4 = (nv_ro16(bios, ramcfg.data + 0x07)); 214 next->bios.ramcfg_10_05);
210 u32 unk804 = (nv_ro08(bios, ramcfg.data + 0x09) & 0xf0) << 16 | 215 ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
211 (nv_ro08(bios, ramcfg.data + 0x03) & 0x0f) << 16 | 216 next->bios.ramcfg_10_07);
212 (nv_ro08(bios, ramcfg.data + 0x09) & 0x0f) | 217 ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
213 0x80000000; 218 next->bios.ramcfg_10_03_0f << 16 |
214 ram_wr32(fuc, 0x1005a0, unk5a0); 219 next->bios.ramcfg_10_09_0f |
215 ram_wr32(fuc, 0x1005a4, unk5a4); 220 0x80000000);
216 ram_wr32(fuc, 0x10f804, unk804);
217 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000); 221 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
218 } else { 222 } else {
219 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000); 223 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
@@ -251,27 +255,26 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
251 ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000); 255 ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000);
252 ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000); 256 ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000);
253 257
254 data = (nv_ro08(bios, ramcfg.data + 0x02) & 0x08) ? 0x00000000 : 0x00001000; 258 ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
255 ram_mask(fuc, 0x100200, 0x00001000, data);
256 259
257 unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010; 260 unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010;
258 unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100; 261 unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
259 unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100; 262 unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
260 if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x20)) 263 if (next->bios.ramcfg_10_02_20)
261 unk714 |= 0xf0000000; 264 unk714 |= 0xf0000000;
262 if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x04)) 265 if (!next->bios.ramcfg_10_02_04)
263 unk714 |= 0x00000010; 266 unk714 |= 0x00000010;
264 ram_wr32(fuc, 0x100714, unk714); 267 ram_wr32(fuc, 0x100714, unk714);
265 268
266 if (nv_ro08(bios, ramcfg.data + 0x02) & 0x01) 269 if (next->bios.ramcfg_10_02_01)
267 unk71c |= 0x00000100; 270 unk71c |= 0x00000100;
268 ram_wr32(fuc, 0x10071c, unk71c); 271 ram_wr32(fuc, 0x10071c, unk71c);
269 272
270 if (nv_ro08(bios, ramcfg.data + 0x02) & 0x02) 273 if (next->bios.ramcfg_10_02_02)
271 unk718 |= 0x00000100; 274 unk718 |= 0x00000100;
272 ram_wr32(fuc, 0x100718, unk718); 275 ram_wr32(fuc, 0x100718, unk718);
273 276
274 if (nv_ro08(bios, ramcfg.data + 0x02) & 0x10) 277 if (next->bios.ramcfg_10_02_10)
275 ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/ 278 ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/
276 279
277 ram_mask(fuc, mr[0], 0x100, 0x100); 280 ram_mask(fuc, mr[0], 0x100, 0x100);
@@ -283,9 +286,9 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
283 ram_nsec(fuc, 12000); 286 ram_nsec(fuc, 12000);
284 287
285 ram_wr32(fuc, 0x611200, 0x00003330); 288 ram_wr32(fuc, 0x611200, 0x00003330);
286 if ( (nv_ro08(bios, rammap.data + 0x04) & 0x02)) 289 if (next->bios.rammap_10_04_02)
287 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800); 290 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
288 if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) { 291 if (next->bios.ramcfg_10_02_10) {
289 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180); 292 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
290 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000); 293 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
291 } else { 294 } else {
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
index b5b043238e6c..bb1eb8f3e639 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
@@ -23,7 +23,6 @@
23 * Ben Skeggs 23 * Ben Skeggs
24 */ 24 */
25 25
26#include <subdev/bios.h>
27#include "priv.h" 26#include "priv.h"
28 27
29struct ramxlat { 28struct ramxlat {
@@ -61,19 +60,18 @@ ramddr2_wr[] = {
61int 60int
62nouveau_sddr2_calc(struct nouveau_ram *ram) 61nouveau_sddr2_calc(struct nouveau_ram *ram)
63{ 62{
64 struct nouveau_bios *bios = nouveau_bios(ram);
65 int CL, WR, DLL = 0, ODT = 0; 63 int CL, WR, DLL = 0, ODT = 0;
66 64
67 switch (!!ram->timing.data * ram->timing.version) { 65 switch (ram->next->bios.timing_ver) {
68 case 0x10: 66 case 0x10:
69 CL = nv_ro08(bios, ram->timing.data + 0x02); 67 CL = ram->next->bios.timing_10_CL;
70 WR = nv_ro08(bios, ram->timing.data + 0x00); 68 WR = ram->next->bios.timing_10_WR;
71 DLL = !(nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x40); 69 DLL = !ram->next->bios.ramcfg_10_02_40;
72 ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x03; 70 ODT = ram->next->bios.timing_10_ODT & 3;
73 break; 71 break;
74 case 0x20: 72 case 0x20:
75 CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f; 73 CL = (ram->next->bios.timing[1] & 0x0000001f);
76 WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f; 74 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
77 break; 75 break;
78 default: 76 default:
79 return -ENOSYS; 77 return -ENOSYS;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
index 3d77fc5add77..83949b11833a 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
@@ -23,7 +23,6 @@
23 * Roy Spliet <rspliet@eclipso.eu> 23 * Roy Spliet <rspliet@eclipso.eu>
24 */ 24 */
25 25
26#include <subdev/bios.h>
27#include "priv.h" 26#include "priv.h"
28 27
29struct ramxlat { 28struct ramxlat {
@@ -70,25 +69,19 @@ ramddr3_cwl[] = {
70int 69int
71nouveau_sddr3_calc(struct nouveau_ram *ram) 70nouveau_sddr3_calc(struct nouveau_ram *ram)
72{ 71{
73 struct nouveau_bios *bios = nouveau_bios(ram);
74 int CWL, CL, WR, DLL = 0, ODT = 0; 72 int CWL, CL, WR, DLL = 0, ODT = 0;
75 u8 ver;
76 73
77 ver = !!ram->timing.data * ram->timing.version; 74 switch (ram->next->bios.timing_ver) {
78 if (ram->next)
79 ver = ram->next->bios.timing_ver;
80
81 switch (ver) {
82 case 0x10: 75 case 0x10:
83 if (ram->timing.size < 0x17) { 76 if (ram->next->bios.timing_hdr < 0x17) {
84 /* XXX: NV50: Get CWL from the timing register */ 77 /* XXX: NV50: Get CWL from the timing register */
85 return -ENOSYS; 78 return -ENOSYS;
86 } 79 }
87 CWL = nv_ro08(bios, ram->timing.data + 0x13); 80 CWL = ram->next->bios.timing_10_CWL;
88 CL = nv_ro08(bios, ram->timing.data + 0x02); 81 CL = ram->next->bios.timing_10_CL;
89 WR = nv_ro08(bios, ram->timing.data + 0x00); 82 WR = ram->next->bios.timing_10_WR;
90 DLL = !(nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x40); 83 DLL = !ram->next->bios.ramcfg_10_02_40;
91 ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x07; 84 ODT = ram->next->bios.timing_10_ODT;
92 break; 85 break;
93 case 0x20: 86 case 0x20:
94 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; 87 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 22:13:09 -0400