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authorGreg Kroah-Hartman <gregkh@suse.de>2009-06-03 12:47:57 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-06-19 14:00:56 -0400
commitc0a5962f761b5c7c312d829c16c2856be6d494db (patch)
tree931a911792b9fdbad3bb634508c4411a5a3c14dc
parent482612afc611a504ef7f0e51022d381876ee3cca (diff)
Staging: pata_rdc: remove function prototypes
Move code around so we do not need the function prototypes anymore. Cc: Kevin Huang <Kevin.Huang@rdc.com.tw> Cc: Tomy Wang <Tomy.Wang@rdc.com.tw> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat
-rw-r--r--drivers/staging/pata_rdc/pata_rdc.c825
-rw-r--r--drivers/staging/pata_rdc/pata_rdc.h30
2 files changed, 402 insertions, 453 deletions
diff --git a/drivers/staging/pata_rdc/pata_rdc.c b/drivers/staging/pata_rdc/pata_rdc.c
index 5d52373eeec0..ab0e1cce40ca 100644
--- a/drivers/staging/pata_rdc/pata_rdc.c
+++ b/drivers/staging/pata_rdc/pata_rdc.c
@@ -36,50 +36,9 @@ static const struct pci_device_id rdc_pata_id_table[] = {
36 { 0x17F3, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31012}, 36 { 0x17F3, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31012},
37 { } /* terminate list */ 37 { } /* terminate list */
38}; 38};
39
40MODULE_LICENSE("GPL");
41MODULE_AUTHOR("this version author is RDC"); /* replace "RDC" with the last maintainer. */
42MODULE_DESCRIPTION("RDC PCI IDE Driver");
43MODULE_DEVICE_TABLE(pci, rdc_pata_id_table); 39MODULE_DEVICE_TABLE(pci, rdc_pata_id_table);
44MODULE_VERSION(DRIVER_VERSION);
45
46/* a pci driver */
47static struct pci_driver rdc_pata_driver = {
48 .name = DRIVER_NAME,
49 .id_table = rdc_pata_id_table,
50 .probe = rdc_init_one,
51 .remove = ata_pci_remove_one,
52#ifdef CONFIG_PM
53 .suspend = ata_pci_device_suspend,
54 .resume = ata_pci_device_resume,
55#endif
56};
57 40
58static unsigned int in_module_init = 1; /* hotplugging check??? */ 41static unsigned int in_module_init = 1; /* hotplugging check??? */
59static int __init pata_rdc_init(void)
60{
61 int rc;
62
63 dbgprintf("pata_rdc_init\n");
64 rc = pci_register_driver(&rdc_pata_driver);
65 if (rc) {
66 dbgprintf("pata_rdc_init faile\n");
67 return rc;
68 }
69
70 in_module_init = 0;
71
72 return 0;
73}
74
75static void __exit pata_rdc_exit(void)
76{
77 dbgprintf("pata_rdc_exit\n");
78 pci_unregister_driver(&rdc_pata_driver);
79}
80
81module_init(pata_rdc_init);
82module_exit(pata_rdc_exit);
83 42
84/* ata device data */ 43/* ata device data */
85 44
@@ -89,387 +48,6 @@ static struct pci_bits ATA_Decode_Enable_Bits[] = {
89 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */ 48 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port (Channel) 1 */
90}; 49};
91 50
92/* pata host template */
93static struct scsi_host_template rdc_pata_sht = {
94 ATA_BMDMA_SHT(DRIVER_NAME),
95};
96
97static const struct ata_port_operations rdc_pata_ops = {
98 .inherits = &ata_bmdma_port_ops,
99
100 .port_start = rdc_pata_port_start,
101 .port_stop = rdc_pata_port_stop,
102 .prereset = rdc_pata_prereset,
103 .cable_detect = rdc_pata_cable_detect,
104 .set_piomode = rdc_pata_set_piomode,
105 .set_dmamode = rdc_pata_set_dmamode,
106};
107
108static struct ata_port_info rdc_pata_port_info[] = {
109 [RDC_17F31011] = {
110 .flags = ATA_FLAG_SLAVE_POSS,
111 .pio_mask = 0x1f, /* pio0-4 */
112 .mwdma_mask = 0x07, /* mwdma0-2 */
113 .udma_mask = ATA_UDMA5, /* udma0-5 */
114 .port_ops = &rdc_pata_ops,
115 },
116
117 [RDC_17F31012] = {
118 .flags = ATA_FLAG_SLAVE_POSS,
119 .pio_mask = 0x1f, /* pio0-4 */
120 .mwdma_mask = 0x07, /* mwdma0-2 */
121 .udma_mask = ATA_UDMA5, /* udma0-5 */
122 .port_ops = &rdc_pata_ops,
123 },
124};
125
126
127
128
129/* callback function for pci_driver */
130
131/**
132 * Register ATA PCI device with kernel services
133 * @pdev: PCI device to register
134 * @ent: Entry in sch_pci_tbl matching with @pdev
135 *
136 * LOCKING:
137 * Inherited from PCI layer (may sleep).
138 *
139 * RETURNS:
140 * Zero on success, or -ERRNO value.
141 */
142static int __devinit rdc_init_one(struct pci_dev *pdev,
143 const struct pci_device_id *ent)
144{
145 /*struct device *dev = &pdev->dev; */
146 struct ata_port_info port_info[2];
147 const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] };
148
149 int rc;
150
151 dbgprintf("rdc_init_one\n");
152
153 /* no hotplugging support (FIXME) */ /* why??? */
154 if (!in_module_init) {
155 dbgprintf("rdc_init_one in_module_init == 0 failed \n");
156 return -ENODEV;
157 }
158 port_info[0] = rdc_pata_port_info[ent->driver_data];
159 port_info[1] = rdc_pata_port_info[ent->driver_data];
160
161 /* enable device and prepare host */
162 rc = pci_enable_device(pdev);
163 if (rc) {
164 dbgprintf("rdc_init_one pci_enable_device failed \n");
165 return rc;
166 }
167 /* initialize controller */
168
169 pci_intx(pdev, 1); /* enable interrupt */
170
171 return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
172}
173
174/* callback function for ata_port */
175
176/**
177 * Set port up for dma.
178 * @ap: Port to initialize
179 *
180 * Called just after data structures for each port are
181 * initialized. Allocates space for PRD table if the device
182 * is DMA capable SFF.
183
184 Some drivers also use this entry point as a chance to allocate driverprivate
185 memory for ap->private_data.
186
187 *
188 * May be used as the port_start() entry in ata_port_operations.
189 *
190 * LOCKING:
191 * Inherited from caller.
192 */
193static int rdc_pata_port_start(struct ata_port *ap)
194{
195 uint Channel;
196
197 Channel = ap->port_no;
198 dbgprintf("rdc_pata_port_start Channel: %u \n", Channel);
199 if (ap->ioaddr.bmdma_addr) {
200 return ata_port_start(ap);
201 } else {
202 dbgprintf("rdc_pata_port_start return 0 !!!\n");
203 return 0;
204 }
205}
206
207static void rdc_pata_port_stop(struct ata_port *ap)
208{
209 uint Channel;
210
211 Channel = ap->port_no;
212
213 dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel);
214}
215
216/**
217 * prereset for PATA host controller
218 * @link: Target link
219 * @deadline: deadline jiffies for the operation
220 *
221 * LOCKING:
222 * None (inherited from caller).
223 */
224static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
225{
226 struct pci_dev *pdev;
227 struct ata_port *ap;
228 uint Channel;
229
230 dbgprintf("rdc_pata_prereset\n");
231
232 ap = link->ap;
233 pdev = to_pci_dev(ap->host->dev);
234
235 Channel = ap->port_no;
236
237 /* test ATA Decode Enable Bits, should be enable. */
238 if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) {
239 dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel);
240 return -ENOENT;
241 } else {
242 dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel);
243 return ata_std_prereset(link, deadline);
244 }
245}
246
247/**
248 * Probe host controller cable detect info
249 * @ap: Port for which cable detect info is desired
250 *
251 * Read cable indicator from ATA PCI device's PCI config
252 * register. This register is normally set by firmware (BIOS).
253 *
254 * LOCKING:
255 * None (inherited from caller).
256 */
257static int rdc_pata_cable_detect(struct ata_port *ap)
258{
259 struct pci_dev *pdev;
260 uint Channel;
261 uint Mask;
262 u32 u32Value;
263
264 dbgprintf("rdc_pata_cable_detect\n");
265
266 pdev = to_pci_dev(ap->host->dev);
267
268 Channel = ap->port_no;
269
270 if (Channel == 0)
271 Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report;
272 else
273 Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report;
274
275 /* check BIOS cable detect results */
276 pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
277
278 if ((u32Value & Mask) == 0) {
279 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel);
280 return ATA_CBL_PATA40;
281 } else {
282 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel);
283 return ATA_CBL_PATA80;
284 }
285}
286
287/**
288 * Initialize host controller PATA PIO timings
289 * @ap: Port whose timings we are configuring
290 * @adev: um
291 *
292 * Set PIO mode for device, in host controller PCI config space.
293 *
294 * LOCKING:
295 * None (inherited from caller).
296 */
297static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev)
298{
299 struct pci_dev *pdev;
300 uint Channel;
301 uint DeviceID;
302 uint PIOTimingMode;
303 uint PrefetchPostingEnable;
304
305 dbgprintf("rdc_pata_set_piomode\n");
306
307 pdev = to_pci_dev(ap->host->dev);
308
309 Channel = ap->port_no;
310 DeviceID = adev->devno;
311 /*
312 * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
313 * XFER_PIO_2, XFER_PIO_3...
314 */
315 PIOTimingMode = adev->pio_mode - XFER_PIO_0;
316
317 if (adev->class == ATA_DEV_ATA) {
318 PrefetchPostingEnable = TRUE;
319 } else {
320 /* ATAPI, CD DVD Rom */
321 PrefetchPostingEnable = FALSE;
322 }
323
324 /* PIO configuration clears DTE unconditionally. It will be
325 * programmed in set_dmamode which is guaranteed to be called
326 * after set_piomode if any DMA mode is available.
327 */
328
329 /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
330 * selected */
331
332 if (Channel == 0) {
333 ATAHostAdapter_SetPrimaryPIO(
334 pdev,
335 DeviceID,
336 PIOTimingMode,
337 TRUE,/* DMAEnable, */
338 PrefetchPostingEnable
339 );
340
341 ATAHostAdapter_SetPrimaryUDMA(
342 pdev,
343 DeviceID,
344 FALSE,/* UDMAEnable, */
345 UDMA0
346 );
347 } else {
348 ATAHostAdapter_SetSecondaryPIO(
349 pdev,
350 DeviceID,
351 PIOTimingMode,
352 TRUE,/* DMAEnable, */
353 PrefetchPostingEnable
354 );
355
356 ATAHostAdapter_SetSecondaryUDMA(
357 pdev,
358 DeviceID,
359 FALSE,/* UDMAEnable, */
360 UDMA0
361 );
362 }
363 dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode);
364}
365
366/**
367 * Initialize host controller PATA DMA timings
368 * @ap: Port whose timings we are configuring
369 * @adev: um
370 *
371 * Set MW/UDMA mode for device, in host controller PCI config space.
372 *
373 * LOCKING:
374 * None (inherited from caller).
375 */
376static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
377{
378 struct pci_dev *pdev;
379 uint Channel;
380 uint DeviceID;
381 uint PIOTimingMode;
382 uint PrefetchPostingEnable;
383 uint DMATimingMode;
384 uint UDMAEnable;
385
386 dbgprintf("rdc_pata_set_dmamode\n");
387
388 pdev = to_pci_dev(ap->host->dev);
389
390 Channel = ap->port_no;
391 DeviceID = adev->devno;
392 PIOTimingMode = adev->pio_mode - XFER_PIO_0; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
393 DMATimingMode = adev->dma_mode; /* UDMA or MDMA */
394
395 if (adev->class == ATA_DEV_ATA) {
396 PrefetchPostingEnable = TRUE;
397 } else {
398 /* ATAPI, CD DVD Rom */
399 PrefetchPostingEnable = FALSE;
400 }
401
402 if (ap->udma_mask == 0) {
403 /* ata_port dont support udma. depend on hardware spec. */
404 UDMAEnable = FALSE;
405 } else {
406 UDMAEnable = TRUE;
407 }
408
409 /*if (ap->mdma_mask == 0) {
410 }*/
411
412 if (Channel == 0) {
413 if (DMATimingMode >= XFER_UDMA_0) {
414 /* UDMA */
415 ATAHostAdapter_SetPrimaryPIO(pdev,
416 DeviceID,
417 PIOTimingMode,
418 TRUE,/*DMAEnable,*/
419 PrefetchPostingEnable);
420
421 ATAHostAdapter_SetPrimaryUDMA(pdev,
422 DeviceID,
423 UDMAEnable,
424 DMATimingMode - XFER_UDMA_0);
425 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
426 } else {
427 /* MDMA */
428 ATAHostAdapter_SetPrimaryPIO(pdev,
429 DeviceID,
430 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
431 TRUE,/*DMAEnable,*/
432 PrefetchPostingEnable);
433
434 ATAHostAdapter_SetPrimaryUDMA(pdev,
435 DeviceID,
436 FALSE,/*UDMAEnable,*/
437 UDMA0);
438 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
439 }
440 } else {
441 if (DMATimingMode >= XFER_UDMA_0) {
442 /* UDMA */
443 ATAHostAdapter_SetSecondaryPIO(pdev,
444 DeviceID,
445 PIOTimingMode,
446 TRUE,/*DMAEnable,*/
447 PrefetchPostingEnable);
448
449 ATAHostAdapter_SetSecondaryUDMA(pdev,
450 DeviceID,
451 UDMAEnable,
452 DMATimingMode - XFER_UDMA_0);
453 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
454 } else {
455 /* MDMA */
456 ATAHostAdapter_SetSecondaryPIO(pdev,
457 DeviceID,
458 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
459 TRUE,/*DMAEnable,*/
460 PrefetchPostingEnable);
461
462 ATAHostAdapter_SetSecondaryUDMA(pdev,
463 DeviceID,
464 FALSE,/*UDMAEnable,*/
465 UDMA0);
466 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
467 }
468 }
469}
470
471/* modified PCIDeviceIO code. */
472
473static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer) 51static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
474{ 52{
475 uint funcresult; 53 uint funcresult;
@@ -518,7 +96,6 @@ funcexit:
518 return funcresult; 96 return funcresult;
519} 97}
520 98
521/* modified ATAHostAdapter code. */
522static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID, 99static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID,
523 uint PIOTimingMode, uint DMAEnable, 100 uint PIOTimingMode, uint DMAEnable,
524 uint PrefetchPostingEnable) 101 uint PrefetchPostingEnable)
@@ -1064,3 +641,405 @@ static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID,
1064funcexit: 641funcexit:
1065 return funcresult; 642 return funcresult;
1066} 643}
644
645/**
646 * Set port up for dma.
647 * @ap: Port to initialize
648 *
649 * Called just after data structures for each port are
650 * initialized. Allocates space for PRD table if the device
651 * is DMA capable SFF.
652
653 Some drivers also use this entry point as a chance to allocate driverprivate
654 memory for ap->private_data.
655
656 *
657 * May be used as the port_start() entry in ata_port_operations.
658 *
659 * LOCKING:
660 * Inherited from caller.
661 */
662static int rdc_pata_port_start(struct ata_port *ap)
663{
664 uint Channel;
665
666 Channel = ap->port_no;
667 dbgprintf("rdc_pata_port_start Channel: %u \n", Channel);
668 if (ap->ioaddr.bmdma_addr) {
669 return ata_port_start(ap);
670 } else {
671 dbgprintf("rdc_pata_port_start return 0 !!!\n");
672 return 0;
673 }
674}
675
676static void rdc_pata_port_stop(struct ata_port *ap)
677{
678 uint Channel;
679
680 Channel = ap->port_no;
681
682 dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel);
683}
684
685/**
686 * prereset for PATA host controller
687 * @link: Target link
688 * @deadline: deadline jiffies for the operation
689 *
690 * LOCKING:
691 * None (inherited from caller).
692 */
693static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
694{
695 struct pci_dev *pdev;
696 struct ata_port *ap;
697 uint Channel;
698
699 dbgprintf("rdc_pata_prereset\n");
700
701 ap = link->ap;
702 pdev = to_pci_dev(ap->host->dev);
703
704 Channel = ap->port_no;
705
706 /* test ATA Decode Enable Bits, should be enable. */
707 if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) {
708 dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel);
709 return -ENOENT;
710 } else {
711 dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel);
712 return ata_std_prereset(link, deadline);
713 }
714}
715
716/**
717 * Probe host controller cable detect info
718 * @ap: Port for which cable detect info is desired
719 *
720 * Read cable indicator from ATA PCI device's PCI config
721 * register. This register is normally set by firmware (BIOS).
722 *
723 * LOCKING:
724 * None (inherited from caller).
725 */
726static int rdc_pata_cable_detect(struct ata_port *ap)
727{
728 struct pci_dev *pdev;
729 uint Channel;
730 uint Mask;
731 u32 u32Value;
732
733 dbgprintf("rdc_pata_cable_detect\n");
734
735 pdev = to_pci_dev(ap->host->dev);
736
737 Channel = ap->port_no;
738
739 if (Channel == 0)
740 Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report;
741 else
742 Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report;
743
744 /* check BIOS cable detect results */
745 pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
746
747 if ((u32Value & Mask) == 0) {
748 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel);
749 return ATA_CBL_PATA40;
750 } else {
751 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel);
752 return ATA_CBL_PATA80;
753 }
754}
755
756/**
757 * Initialize host controller PATA PIO timings
758 * @ap: Port whose timings we are configuring
759 * @adev: um
760 *
761 * Set PIO mode for device, in host controller PCI config space.
762 *
763 * LOCKING:
764 * None (inherited from caller).
765 */
766static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev)
767{
768 struct pci_dev *pdev;
769 uint Channel;
770 uint DeviceID;
771 uint PIOTimingMode;
772 uint PrefetchPostingEnable;
773
774 dbgprintf("rdc_pata_set_piomode\n");
775
776 pdev = to_pci_dev(ap->host->dev);
777
778 Channel = ap->port_no;
779 DeviceID = adev->devno;
780 /*
781 * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
782 * XFER_PIO_2, XFER_PIO_3...
783 */
784 PIOTimingMode = adev->pio_mode - XFER_PIO_0;
785
786 if (adev->class == ATA_DEV_ATA) {
787 PrefetchPostingEnable = TRUE;
788 } else {
789 /* ATAPI, CD DVD Rom */
790 PrefetchPostingEnable = FALSE;
791 }
792
793 /* PIO configuration clears DTE unconditionally. It will be
794 * programmed in set_dmamode which is guaranteed to be called
795 * after set_piomode if any DMA mode is available.
796 */
797
798 /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
799 * selected */
800
801 if (Channel == 0) {
802 ATAHostAdapter_SetPrimaryPIO(
803 pdev,
804 DeviceID,
805 PIOTimingMode,
806 TRUE,/* DMAEnable, */
807 PrefetchPostingEnable
808 );
809
810 ATAHostAdapter_SetPrimaryUDMA(
811 pdev,
812 DeviceID,
813 FALSE,/* UDMAEnable, */
814 UDMA0
815 );
816 } else {
817 ATAHostAdapter_SetSecondaryPIO(
818 pdev,
819 DeviceID,
820 PIOTimingMode,
821 TRUE,/* DMAEnable, */
822 PrefetchPostingEnable
823 );
824
825 ATAHostAdapter_SetSecondaryUDMA(
826 pdev,
827 DeviceID,
828 FALSE,/* UDMAEnable, */
829 UDMA0
830 );
831 }
832 dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode);
833}
834
835/**
836 * Initialize host controller PATA DMA timings
837 * @ap: Port whose timings we are configuring
838 * @adev: um
839 *
840 * Set MW/UDMA mode for device, in host controller PCI config space.
841 *
842 * LOCKING:
843 * None (inherited from caller).
844 */
845static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
846{
847 struct pci_dev *pdev;
848 uint Channel;
849 uint DeviceID;
850 uint PIOTimingMode;
851 uint PrefetchPostingEnable;
852 uint DMATimingMode;
853 uint UDMAEnable;
854
855 dbgprintf("rdc_pata_set_dmamode\n");
856
857 pdev = to_pci_dev(ap->host->dev);
858
859 Channel = ap->port_no;
860 DeviceID = adev->devno;
861 PIOTimingMode = adev->pio_mode - XFER_PIO_0; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
862 DMATimingMode = adev->dma_mode; /* UDMA or MDMA */
863
864 if (adev->class == ATA_DEV_ATA) {
865 PrefetchPostingEnable = TRUE;
866 } else {
867 /* ATAPI, CD DVD Rom */
868 PrefetchPostingEnable = FALSE;
869 }
870
871 if (ap->udma_mask == 0) {
872 /* ata_port dont support udma. depend on hardware spec. */
873 UDMAEnable = FALSE;
874 } else {
875 UDMAEnable = TRUE;
876 }
877
878 /*if (ap->mdma_mask == 0) {
879 }*/
880
881 if (Channel == 0) {
882 if (DMATimingMode >= XFER_UDMA_0) {
883 /* UDMA */
884 ATAHostAdapter_SetPrimaryPIO(pdev,
885 DeviceID,
886 PIOTimingMode,
887 TRUE,/*DMAEnable,*/
888 PrefetchPostingEnable);
889
890 ATAHostAdapter_SetPrimaryUDMA(pdev,
891 DeviceID,
892 UDMAEnable,
893 DMATimingMode - XFER_UDMA_0);
894 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
895 } else {
896 /* MDMA */
897 ATAHostAdapter_SetPrimaryPIO(pdev,
898 DeviceID,
899 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
900 TRUE,/*DMAEnable,*/
901 PrefetchPostingEnable);
902
903 ATAHostAdapter_SetPrimaryUDMA(pdev,
904 DeviceID,
905 FALSE,/*UDMAEnable,*/
906 UDMA0);
907 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
908 }
909 } else {
910 if (DMATimingMode >= XFER_UDMA_0) {
911 /* UDMA */
912 ATAHostAdapter_SetSecondaryPIO(pdev,
913 DeviceID,
914 PIOTimingMode,
915 TRUE,/*DMAEnable,*/
916 PrefetchPostingEnable);
917
918 ATAHostAdapter_SetSecondaryUDMA(pdev,
919 DeviceID,
920 UDMAEnable,
921 DMATimingMode - XFER_UDMA_0);
922 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
923 } else {
924 /* MDMA */
925 ATAHostAdapter_SetSecondaryPIO(pdev,
926 DeviceID,
927 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
928 TRUE,/*DMAEnable,*/
929 PrefetchPostingEnable);
930
931 ATAHostAdapter_SetSecondaryUDMA(pdev,
932 DeviceID,
933 FALSE,/*UDMAEnable,*/
934 UDMA0);
935 dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
936 }
937 }
938}
939
940/* pata host template */
941static struct scsi_host_template rdc_pata_sht = {
942 ATA_BMDMA_SHT(DRIVER_NAME),
943};
944
945static const struct ata_port_operations rdc_pata_ops = {
946 .inherits = &ata_bmdma_port_ops,
947
948 .port_start = rdc_pata_port_start,
949 .port_stop = rdc_pata_port_stop,
950 .prereset = rdc_pata_prereset,
951 .cable_detect = rdc_pata_cable_detect,
952 .set_piomode = rdc_pata_set_piomode,
953 .set_dmamode = rdc_pata_set_dmamode,
954};
955
956static struct ata_port_info rdc_pata_port_info[] = {
957 [RDC_17F31011] = {
958 .flags = ATA_FLAG_SLAVE_POSS,
959 .pio_mask = 0x1f, /* pio0-4 */
960 .mwdma_mask = 0x07, /* mwdma0-2 */
961 .udma_mask = ATA_UDMA5, /* udma0-5 */
962 .port_ops = &rdc_pata_ops,
963 },
964
965 [RDC_17F31012] = {
966 .flags = ATA_FLAG_SLAVE_POSS,
967 .pio_mask = 0x1f, /* pio0-4 */
968 .mwdma_mask = 0x07, /* mwdma0-2 */
969 .udma_mask = ATA_UDMA5, /* udma0-5 */
970 .port_ops = &rdc_pata_ops,
971 },
972};
973
974static int __devinit rdc_init_one(struct pci_dev *pdev,
975 const struct pci_device_id *ent)
976{
977 /*struct device *dev = &pdev->dev; */
978 struct ata_port_info port_info[2];
979 const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] };
980
981 int rc;
982
983 dbgprintf("rdc_init_one\n");
984
985 /* no hotplugging support (FIXME) */ /* why??? */
986 if (!in_module_init) {
987 dbgprintf("rdc_init_one in_module_init == 0 failed \n");
988 return -ENODEV;
989 }
990 port_info[0] = rdc_pata_port_info[ent->driver_data];
991 port_info[1] = rdc_pata_port_info[ent->driver_data];
992
993 /* enable device and prepare host */
994 rc = pci_enable_device(pdev);
995 if (rc) {
996 dbgprintf("rdc_init_one pci_enable_device failed \n");
997 return rc;
998 }
999 /* initialize controller */
1000
1001 pci_intx(pdev, 1); /* enable interrupt */
1002
1003 return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
1004}
1005
1006/* a pci driver */
1007static struct pci_driver rdc_pata_driver = {
1008 .name = DRIVER_NAME,
1009 .id_table = rdc_pata_id_table,
1010 .probe = rdc_init_one,
1011 .remove = ata_pci_remove_one,
1012#ifdef CONFIG_PM
1013 .suspend = ata_pci_device_suspend,
1014 .resume = ata_pci_device_resume,
1015#endif
1016};
1017
1018static int __init pata_rdc_init(void)
1019{
1020 int rc;
1021
1022 dbgprintf("pata_rdc_init\n");
1023 rc = pci_register_driver(&rdc_pata_driver);
1024 if (rc) {
1025 dbgprintf("pata_rdc_init faile\n");
1026 return rc;
1027 }
1028
1029 in_module_init = 0;
1030
1031 return 0;
1032}
1033
1034static void __exit pata_rdc_exit(void)
1035{
1036 dbgprintf("pata_rdc_exit\n");
1037 pci_unregister_driver(&rdc_pata_driver);
1038}
1039
1040module_init(pata_rdc_init);
1041module_exit(pata_rdc_exit);
1042
1043MODULE_LICENSE("GPL");
1044MODULE_DESCRIPTION("RDC PCI IDE Driver");
1045MODULE_VERSION(DRIVER_VERSION);
diff --git a/drivers/staging/pata_rdc/pata_rdc.h b/drivers/staging/pata_rdc/pata_rdc.h
index 64adca0c53b8..a833339886d9 100644
--- a/drivers/staging/pata_rdc/pata_rdc.h
+++ b/drivers/staging/pata_rdc/pata_rdc.h
@@ -141,34 +141,4 @@ enum rdc_controller_ids {
141 RDC_17F31012 141 RDC_17F31012
142}; 142};
143 143
144/* callback function for driver */
145static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
146
147/* callback function for ata_port */
148static int rdc_pata_port_start(struct ata_port *ap);
149
150static void rdc_pata_port_stop(struct ata_port *ap);
151
152static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline);
153
154static int rdc_pata_cable_detect(struct ata_port *ap);
155
156static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev);
157
158static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev);
159
160/* modified PCIDeviceIO code. */
161static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer);
162
163static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer);
164
165/* modify ATAHostAdapter code */
166static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID, uint PIOTimingMode, uint DMAEnable, uint PrefetchPostingEnable);
167
168static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID, uint PIOTimingMode, uint DMAEnable, uint PrefetchPostingEnable);
169
170static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID, uint UDMAEnable, uint UDMATimingMode);
171
172static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID, uint UDMAEnable, uint UDMATimingMode);
173
174#endif 144#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 12:26:06 -0400